GROUP III-NITRIDE TRANSISTOR WITH CHARGE-INDUCING LAYER
Embodiments of the present disclosure describe apparatuses, methods, and systems of a device such as a transistor. The device includes a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N), a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N), and a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel. Other embodiments may also be described and/or claimed.
1 . An apparatus comprising:
a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N);
a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N);
a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N); and
a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel.
2 . The apparatus of claim 1 , wherein:
the charge-inducing layer has a first bandgap energy;
the barrier layer has a second bandgap energy; and
the first bandgap energy is greater than the second bandgap energy.
3 . The apparatus of claim 1 , wherein:
the charge-inducing layer has a first polarization;
the barrier layer has a second polarization; and
the first polarization is greater than the second polarization.
4 . The apparatus of claim 1 , wherein:
the barrier layer has a thickness that inhibits formation of a two-dimensional electron gas (2DEG) at a gate region disposed between the gate terminal and the buffer layer; and
the gate terminal is configured to control switching of an Enhancement mode (e-mode) high electron mobility transistor (HEMT) switch device of a power amplifier.
5 . The apparatus of claim 1 , further comprising:
a cap layer disposed on the charge-inducing layer, the cap layer including aluminum (Al), gallium (Ga), and nitrogen (N).
6 . The apparatus of claim 5 , wherein:
the buffer layer includes gallium nitride (GaN);
the barrier layer and the cap layer include aluminum gallium nitride (Al x Ga 1-x N) where x has a value less than or equal to 0.2 representing relative quantities of the respective elements; and
the charge-inducing layer includes indium aluminum nitride (In y Al 1-y N) where y has a value less than or equal to 0.2 representing relative quantities of the respective elements.
7 . The apparatus of claim 6 , wherein:
the barrier layer has a thickness that is greater than or equal to 30 angstroms;
the charge-inducing layer has a thickness that is less than or equal to 30 angstroms; and
the cap layer has a thickness that is less than or equal to 10,000 angstroms.
8 . The apparatus of claim 1 , wherein the gate terminal includes a gate electrode that is coupled with material of the barrier layer to form a Schottky junction.
9 . The apparatus of claim 1 , wherein:
the gate terminal includes a gate electrode and a gate insulator coupled with material of the barrier layer to form a metal-insulator-semiconductor (MIS) junction.
10 . The apparatus of claim 1 , further comprising:
a source coupled with the charge-inducing layer; and
a drain coupled with the charge-inducing layer, wherein the source and the drain extend through the charge-inducing layer and the barrier layer into the buffer layer.
11 . The apparatus of claim 10 , further comprising:
a dielectric material disposed on the charge-inducing layer, the dielectric material encapsulating a portion of the gate terminal.
12 . The apparatus of claim 11 , wherein:
the gate terminal is a T-shaped field-plate gate; and
the gate terminal includes nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), or gold (Au).
13 . The apparatus of claim 12 , further comprising:
a field-plate disposed on the dielectric material, the field-plate being electrically coupled with the source and capacitively coupled with the gate terminal through the dielectric material.
14 . The apparatus of claim 1 , further comprising:
the substrate, the substrate including silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium nitride (GaN), diamond (C), silicon oxide (SiO 2 ), or aluminum nitride (AlN).
15 . The apparatus of claim 14 , wherein:
the buffer layer is epitaxially coupled with the substrate;
the barrier layer is epitaxially coupled with the buffer layer; and
the charge-inducing layer is epitaxially coupled with the barrier layer.
16 . The apparatus of claim 15 , wherein the buffer layer, the barrier layer, or the charge-inducing layer is composed of multiple layers.
17 . A method comprising:
forming a buffer layer on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N);
forming a barrier layer on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N);
forming a charge-inducing layer on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N); and
forming a gate terminal in the charge-inducing layer, the gate terminal being coupled with the barrier layer to control the channel.
18 . The method of claim 17 , wherein:
forming the buffer layer includes epitaxially depositing a buffer layer material on the substrate;
forming the barrier layer includes epitaxially depositing a barrier layer material on the buffer layer; and
forming the charge-inducing layer includes epitaxially depositing a charge-inducing layer material on the barrier layer, wherein the charge-inducing layer has a first polarization, the barrier layer has a second polarization and the first polarization is greater than the second polarization.
19 . The method of claim 18 , wherein forming the charge-inducing layer includes epitaxially depositing a charge-inducing layer material on the barrier layer, wherein the charge-inducing layer has a first bandgap energy, the barrier layer has a second bandgap energy and the first bandgap energy is greater than the second bandgap energy.
20 . The method of claim 18 , further comprising
forming a cap layer on the charge-inducing layer by epitaxially depositing a cap layer material on the charge-inducing layer, the cap layer including aluminum (Al), gallium (Ga), and nitrogen (N).
21 . The method of claim 20 , wherein:
the buffer layer material includes gallium nitride (GaN);
the barrier layer material and the cap layer material include aluminum gallium nitride (Al x Ga 1-x N) where x has a value less than or equal to 0.2 representing relative quantities of the respective elements; and
the charge-inducing layer material includes indium aluminum nitride (In y Al 1-y N) where y has a value less than or equal to 0.2 representing relative quantities of the respective elements.
22 . The method of claim 21 , wherein:
forming the barrier layer provides a barrier layer thickness that is less than or equal to 60 angstroms;
forming the charge-inducing layer provides a charge-inducing layer thickness that is less than or equal to 30 angstroms; and
forming the cap layer provides a cap layer thickness that is less than or equal to 10,000 angstroms.
23 . The method of claim 22 , wherein:
the barrier layer thickness inhibits formation of a two-dimensional electron gas (2DEG) at a gate region disposed between the gate terminal and the buffer layer; and
the gate terminal is configured to control switching of an Enhancement mode (e-mode) high electron mobility transistor (HEMT) device.
24 . The method of claim 20 , wherein forming the gate terminal comprises:
removing a portion of the cap layer to expose the charge-inducing layer; and
removing a portion of the charge-inducing layer.
25 . The method of claim 24 , wherein:
removing the material of the cap layer comprises selectively etching the cap layer material using boron chloride (BCl 3 ) or chlorine (Cl 2 ); and
removing the portion of the charge-inducing layer comprises selectively etching the charge-inducing layer material using potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH).
26 . The method of claim 25 , wherein:
removing the portion of the charge-inducing layer exposes the barrier layer; and
the barrier layer serves as an etch stop layer for the selective etching of the charge-inducing layer material.
27 . The method of claim 25 , wherein forming the gate terminal further comprises:
depositing a gate electrode material in a region where the cap layer material and the charge-inducing layer have been removed, the gate electrode material being coupled with the material of the barrier layer to form a Schottky junction.
28 . The method of claim 25 , wherein forming the gate terminal further comprises:
selectively oxidizing the charge-inducing layer material that is exposed by removing the portion of the charge-inducing layer to form a gate insulator; and
depositing a gate electrode material on the gate insulator, the gate electrode and the gate insulator being coupled with the barrier layer material to form a metal-insulator-semiconductor (MIS) junction.
29 . The method of claim 17 , further comprising:
forming a source and drain coupled with the charge-inducing layer, wherein the source and the drain extend through the charge-inducing layer and the barrier layer into the buffer layer.
30 . The method of claim 29 , further comprising:
depositing a dielectric material on the charge-inducing layer, the dielectric material encapsulating a portion of the gate terminal.
31 . The method of claim 30 , wherein the gate terminal is a T-shaped field-plate gate, the method further comprising:
forming a field-plate on the dielectric material, the field-plate being electrically coupled with the source and capacitively coupled with the gate terminal through the dielectric material.