Power-on sequencing for an RFID tag
View Patent ↗Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.
1. A sequencing circuit for an RFID circuit comprises:
an input node for receiving an external voltage;
a bandgap circuit coupled to the input node;
a bandgap ready circuit coupled to the bandgap circuit;
a slew filter having an input coupled to the input node and to the bandgap ready circuit;
a filter capacitor coupled to an output of the slew filter; and
an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal.
2. The sequencing circuit of claim 1 wherein the RFID circuit comprises a ferroelectric RFID circuit.
3. The sequencing circuit of claim 1 further comprising a plurality of delay circuits for introducing a controlled delay between operational modes of the RFID circuit.
4. The sequencing circuit of claim 1 further comprising a plurality of POR cells.
5. The sequencing circuit of claim 4 wherein the plurality of POR cells comprises first and second types of POR cells.
6. The sequencing circuit of claim 5 wherein the POR cells detect the sufficiency of a first power supply voltage.
7. The sequencing circuit of claim 6 wherein the POR cells detect the sufficiency of a second power supply voltage.
8. The sequencing circuit of claim 1 further comprising a digital state machine to monitor a plurality of internal nodes to control a shut-down pulse generator.
9. The sequencing circuit of claim 1 further comprising a plurality of shut-down discharge cells.
10. The sequencing circuit of claim 1 wherein the LDO regulator is coupled to a delay circuit.
11. A sequencing method for an RFID circuit comprises:
receiving an external voltage at an input node;
coupling a bandgap circuit to the input node;
coupling a bandgap ready circuit to the bandgap circuit;
coupling an input node of a slew filter to the input node and to the bandgap ready circuit;
coupling a filter capacitor to an output of the slew filter; and
coupling an input of an LDO regulator to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal.
12. The sequencing method of claim 11 wherein the RFID circuit comprises a ferroelectric RFID circuit.
13. The sequencing method of claim 11 further comprising providing a plurality of delay circuits for introducing a controlled delay between operational modes of the RFID circuit.
14. The sequencing method of claim 11 further comprising providing a plurality of POR cells.
15. The sequencing method of claim 14 wherein the plurality of POR cells comprises first and second types of POR cells.
16. The sequencing method of claim 15 wherein the POR cells detect the sufficiency of a first power supply voltage.
17. The sequencing method of claim 16 wherein the POR cells detect the sufficiency of a second power supply voltage.
18. The sequencing method of claim 11 further comprising providing a digital state machine to monitor a plurality of internal nodes to control a shut-down pulse generator.
19. The sequencing method of claim 11 further comprising a providing a plurality of shut-down discharge cells.
20. The sequencing method of claim 11 wherein the LDO regulator is coupled to a delay circuit.