Transceiver for communicating signal encoded to include clock information
In a transceiver, a clock generator generates a second clock synchronized with a first clock. The second clock has a period corresponding to a duration of one bit of a digital signal. When first transmission data is supplied to the transceiver with being asynchronous to the second clock, a sampling timing generator detects start data of the first transmission data as a start timing, and generates sampling timings based on the first clock in response to the start timing. The sampling timings have intervals each of which is defined to correspond to the period of the second clock. The first sampling timing is spaced from the start timing. A sampling module samples, at each of the sampling timings, the first transmission data, thus generating second transmission data synchronized with the second clock.
1. A transceiver comprising:
a first clock generator configured to locally generate a first clock, the transceiver communicating a digital signal encoded to include information of the first clock through a communication bus;
a second clock generator configured to generate a second clock synchronized with the first clock, the second clock having a period corresponding to a duration of one bit of a digital signal on the communication bus;
a sampling timing generator configured to, when first transmission data is supplied to the transceiver with being asynchronous to the second clock, detect start data of the first transmission data as a start timing, and generate sampling timings in response to the start timing, the sampling timings having intervals each of which is defined to correspond to the period of the second clock, the first sampling timing in the sampling timings being spaced from the start timing;
a first sampling module configured to sample, at each of the sampling timings, the first transmission data, thus generating second transmission data;
a second sampling module configured to sample, at each falling edge of the second clock, the second transmission data generated by the first sampling module, thus generating third transmission data synchronized with the second clock; and
a transmitter configured to encode the third transmission data to a digital signal including information of the first clock, and transmit the digital signal through the communication bus.
2. The transceiver according to claim 1 , wherein the second clock generator is configured to generate a multiplication clock having N level-transition edges as sampling edges within each cycle of the second clock where the N is an integer equal to or greater than 3, and the sampling timing generator is configured to generate a corresponding one of the sampling timings each time a (P+k·N)-th sampling edge of the multiplication clock occurs after detection of the start timing where P=(N+1)/2 when N is an odd number and P=(N+2)/2 when N is an even number, and k is 0, 1, 2, . . ., KLIM where KLIM is an upper limit of the k which is determined based on a length of the transmission data.
3. The transceiver according to claim 1 , wherein the sampling timing generator further comprises a counter configured to count the duration of one bit of the digital signal according to the first clock as a period count value, and
wherein the sampling timing generator is configured to:
generate the first sampling timing at a timing when a half of the period count value corresponding to the duration of one bit of the digital signal is reached by the counter; and
generate, after generation of the first sampling timing, a corresponding one of the remaining sampling timings each time the period count value corresponding to the duration of one bit of the digital signal is reached by the counter.
4. The transceiver according to claim 1 , wherein the sampling timing generator further comprises:
a counter configured to count the duration of one bit of the digital signal according to the first clock as a period count value; and
an offset-value generator configured to generate an interval between a target edge and the start timing, the target edge is a level-transition edge in the second clock occurring immediately before the start timing, and
wherein the sampling timing generator is configured to:
generate the first sampling timing at a timing when a half of the period count value corresponding to the duration of one bit of the digital signal is reached by the counter; and
generate, after generation of the first sampling timing, a corresponding one of the remaining sampling timings each time the sum of the offset value and the half of the period count value is reached by the counter in response to an occurrence of a corresponding level transition edge in the second clock corresponding to the target edge.
5. The transceiver according to claim 1 , wherein the second clock is different from the first clock.
6. The transceiver according to claim 1 , wherein the second sampling module is separate from the first sampling module.
7. The transceiver according to claim 2 , wherein the sampling timing generator comprises:
a start-timing detector configured to detect the start data of the first transmission data as the start timing; and
a generating module configured to measure a period until a (P+k·N)-th sampling edge of the multiplication clock has occurred since detection of the start timing, and generate a corresponding one of the sampling timings each time the period is measured, and
wherein the first sampling module further comprises a first latch configured to latch, at each of the sampling timings, a corresponding bit of the first transmission data, thus generating second transmission data; and
the second sampling module further comprises a second latch connected in series to the first latch and configured to latch a corresponding one of the latched bits of the second transmission data by the first latch at a timing synchronized with each level-transition edge of the second clock, thus generating the third transmission data.
8. The transceiver according to claim 3 , wherein the sampling timing generator further comprises:
a start-timing detector configured to detect the start data of the first transmission data as the start timing; and
a generating module configured to generate a corresponding one of the remaining sampling timings each time the period count value corresponding to the duration of one bit of the digital signal is reached by the counter, and
wherein the first sampling module further comprises
a first latch configured to latch, at each of the sampling timings, a corresponding bit of the first transmission data, thus generating second transmission data; and
the second sampling module further comprises a second latch connected in series to the first latch and configured to latch a corresponding one of the latched bits of the first latch at a timing synchronized with each level-transition edge of the second clock, thus generating the third transmission data.
9. The transceiver according to claim 4 , wherein the sampling timing generator further comprises:
a start-timing detector configured to detect the start data of the first transmission data as the start timing; and
a generating module configured to generate a corresponding one of the remaining sampling timings each time the sum of the offset value and the half of the cyclic-count value is reached by the counter in response to an occurrence of a corresponding level transition edge in the second clock corresponding to the target edge, and
wherein the first sampling module further comprises
a first latch configured to latch, at each of the sampling timings, a corresponding bit of the first transmission data, thus generating second transmission data; and
the second sampling module further comprises a second latch connected in series to the first latch and configured to latch a corresponding one of the latched bits of the first latch at a timing synchronized with each level-transition edge of the second clock, thus generating the third transmission data.
10. A communication system comprising:
a communication bus; and
a plurality of nodes communicably coupled to each other through the bus, each of the plurality of nodes comprising:
a transceiver comprising:
a first clock generator configured to locally generate a first clock, the transceiver communicating a digital signal encoded to include information of the first clock through the communication bus;
a second clock generator configured to generate a second clock synchronized with the first clock, the second clock having a period corresponding to a duration of one bit of a digital signal on the communication bus;
a sampling timing generator configured to, when first transmission data is supplied to the transceiver with being asynchronous to the second clock, detect start data of the first transmission data as a start timing, and generate sampling timings in response to the start timing, the sampling timings having intervals each of which is defined to correspond to the period of the second clock, the first sampling timing in the sampling timings being spaced from the start timing;
a first sampling module configured to sample, at each of the sampling timings, the first transmission data, thus generating second transmission data;
a second sampling module configured to sample at each falling edge of the second clock, the second transmission data generated by the first sampling module, thus generating third transmission data synchronized with the second clock; and
a transmitter configured to encode the third transmission data to a digital signal including information of the first clock, and transmit the digital signal through the communication bus.
11. The communication system according to claim 10 , wherein the second clock generator is configured to generate a multiplication clock having N level-transition edges as sampling edges within each cycle of the second clock where the N is an integer equal to or greater than 3, and the sampling timing generator is configured to generate a corresponding one of the sampling timings each time a (P+k·N)-th sampling edge of the multiplication clock occurs after detection of the start timing where P=(N+1)/2 when N is an odd number and P=(N+2)/2 when N is an even number, and k is 0, 1, 2, . . ., KLIM where KLIM is an upper limit of the k which is determined based on a length of the transmission data.
12. The communication system according to claim 10 , further comprising:
a counter configured to count the duration of one bit of the digital signal according to the first clock as a period count value,
wherein the sampling timing generator is configured to:
generate the first sampling timing at a timing when a half of the period count value corresponding to the duration of one bit of the digital signal is reached by the counter; and
generate, after generation of the first sampling timing, a corresponding one of the remaining sampling timings each time the period count value corresponding to the duration of one bit of the digital signal is reached by the counter.
13. The communication system according to claim 10 , further comprising:
a counter configured to count the duration of one bit of the digital signal according to the first clock as a period count value; and
an offset-value generator configured to generate an interval from a target edge and the start timing, the target edge being a level-transition edge in the second clock occurring immediately before the start timing,
wherein the sampling timing generator is configured to:
generate the first sampling timing at a timing when a half of the period count value corresponding to the duration of one bit of the digital signal is reached by the counter; and
generate, after generation of the first sampling timing, a corresponding one of the remaining sampling timings each time the sum of the offset value and the half of the cyclic-count value is reached by the counter in response to an occurrence of a corresponding level transition edge in the second clock corresponding to the target edge.
14. The transceiver according to claim 10 , wherein the second clock is different from the first clock.
15. The transceiver according to claim 10 , wherein the second sampling module is separate from the first sampling module.