System and method for performing a branch object conversion to program configurable logic circuitry
View Patent ↗A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
1. A method for forming logic circuits from a software encoded logic, the method comprising:
a. Selecting an ordered list of instructions having no overlapping branch logic;
b. Converting the ordered list of instructions into an unordered plurality of software-encoded logic constructs (“constructs”), wherein the plurality of constructs encodes all necessary opcode information and dependency information of the ordered list of instructions; and
c. Applying the plurality of constructs to the design of a digital logic circuit, whereby an internal connectivity and a structure of the digital logic circuit are formed to embody at least some of the opcode information and dependency information of the software encoded logic.
2. The method of claim 1 , wherein the dependency information embodied by the digital logic circuit includes at least one data dependency.
3. The method of claim 1 , wherein the dependency information embodied by the digital logic circuit includes at least one logic dependency.
4. The method of claim 1 , wherein the dependency information embodied by the digital logic circuit includes at least one memory system dependency.
5. The method of claim 1 , wherein the opcode information embodied by the digital logic circuit includes at least one branch instruction.
6. The method of claim 1 , wherein the opcode information embodied by the digital logic circuit includes at least one logical loop process.
7. The method of claim 1 , wherein the opcode information embodied by the digital logic circuit includes at least one logical conditional process.
8. The method of claim 1 , wherein the opcode information embodied by the digital logic circuit includes at least one component hierarchy.
9. The method of claim 1 , wherein at least one opcode instruction of the opcode information is expressed within a software object.
10. The method of claim 1 , wherein at least one opcode instruction of the opcode information is expressed within a construct.
11. A method for programming a computer comprising a parallel execution logic circuitry, the method comprising:
a. Selecting an ordered list of instructions having no overlapping branch logic;
b. Converting the ordered list of instructions into an unordered plurality of software-encoded logic constructs (“constructs”), wherein the plurality of constructs encodes all necessary opcode information and dependency information of the ordered list of instructions; and
c. Converting the unordered plurality of constructs into a machine-executable software program (“machine-code”); and
d. Operating the computer in accordance with the machine-code.
12. The method of claim 11 , wherein dependency information provided in the machine-code includes at least one data dependency.
13. The method of claim 11 , wherein dependency information provided in the machine code includes at least one logic dependency.
14. The method of claim 11 , wherein dependency information provided in the machine code includes at least one memory system dependency.
15. The method of claim 11 , wherein opcode information provided in the machine code includes at least one branch instruction.
16. The method of claim 11 , wherein opcode information provided in the machine code includes at least one logical loop process.
17. The method of claim 11 , wherein opcode provided in the machine-code includes at least one logical conditional process.
18. The method of claim 11 , wherein opcode information provided in the machine code includes at least one component hierarchy.
19. The method of claim 11 , wherein at least one opcode instruction of the opcode information is expressed within a software object.
20. The method of claim 11 , wherein at least one opcode instruction of the opcode information is expressed within a construct.