Semiconductor device
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101 , an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113 , and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101 . The interconnect component 101 has a constitution where an interconnect layer 103 , a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
1. A semiconductor device comprising:
a first memory chip having a main surface, a first electrode and a second electrode on the main surface;
a second memory chip having a third electrode, a fourth electrode, a first electrode penetrating the second memory chip and a second through electrode penetrating the second memory chip;
a logic chip having a first side, a second side opposite the first side, a fifth electrode, a sixth electrode, a seventh electrode and an eighth electrode;
the first memory chip stacked over the second memory chip;
the logic chip formed under the second memory chip;
the first electrode electrically connecting to the first through electrode;
the second electrode electrically connecting to the second through electrode;
the first through electrode electrically connecting to the third electrode;
the second through electrode electrically connecting to the fourth electrode;
the third electrode electrically connecting to the fifth electrode;
the fourth electrode electrically connecting to the sixth electrode;
the fifth electrode and the sixth electrode arrayed in a central area of the logic chip in a cross sectional view;
the seventh electrode arrayed along the first side of the logic chip in the cross section view; and
the eighth electrode arrayed along the second side of the logic chip in the cross section view,
wherein a pitch between the first electrode and the second electrode is equal to a pitch between the fifth electrode and the sixth electrode, and
a pitch between the seventh electrode and the eighth electrode is wider than the pitch between the fifth electrode and the sixth electrode.
2. The semiconductor device according to claim 1 , wherein the first electrode, the first through electrode, the third electrode and the fifth electrode are formed in line along a normal line to the main surface of the first memory chip in cross sectional view, and
the second electrode, the second through electrode, the fourth electrode and the sixth electrode are formed in line along a normal line to the main surface of the first memory chip in cross sectional view.
3. The semiconductor device according to claim 1 ,
wherein the first electrode and the second electrode are arrayed in a central area of the first memory chip in cross sectional view, and
the third electrode, the fourth electrode, the first through electrode and the second through electrode are arrayed in the central area of the second memory chip in cross sectional view.
4. The semiconductor device according to claim 1 ,
wherein the fifth electrode and the sixth electrode are arranged in a minimal interval of not more than 50 μm.
5. The semiconductor device according to claim 1 , further comprising:
an interconnect component mounting the logic chip;
the interconnect component including wirings and a plurality of external electrodes; and
the plurality of external electrodes including a first external electrode and a second external electrode,
wherein the first external electrode is electrically connected to the seventh electrode of the logic chip via the wirings, and
the second external electrode is electrically connected to the eighth electrode of the logic chip via the wirings.
6. The semiconductor device according to claim 5 , wherein the logic chip and the interconnect component are connected by a flip-chip connection.
7. The semiconductor device according to claim 5 , further comprising:
a first underfill resin filling between the interconnect component and the logic chip.
8. The semiconductor device according to claim 7 , further comprising:
a second underfill resin filling between the interconnect component and the second memory chip; and
a third underfill resin filling between the second memory and the first memory chip.
9. The semiconductor device according to claim 8 , further comprising:
a sealing resin covering a surface of said interconnect component, the second underfill resin, the third underfill resin and the first memory chip and the second memory chip.