Path isolation in a memory device
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.
1. An apparatus comprising:
a memory cell of a memory device;
a bit-line coupled to the memory cell;
a word-line coupled to the memory cell;
a bit-line electrode coupled to the bit-line;
a word-line electrode coupled to the word-line;
current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module;
sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the memory cell; and
write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell,
wherein the apparatus is configured to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode, and
wherein the apparatus is configured to provide a capacitance of the word-line electrode that is lower than a capacitance of the bit-line electrode.
2. The apparatus of claim 1 , wherein the current-limiting circuitry comprises a current-mirror circuit.
3. The apparatus of claim 1 , wherein the current-limiting circuitry comprises a transistor gate that is configured to limit a current of the word-line electrode path to a maximum current level.
4. The apparatus of claim 1 , wherein the memory cell is a memory cell of a three-dimensional array of memory cells, the word-line is a first word-line extending in a first dimension of the three-dimensional array, the bit-line extends in a second dimension of the three-dimensional array, and the memory cell is a first memory cell, the apparatus further comprising:
a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and
a second word-line coupled to the word-line electrode and further coupled to the second memory cell, wherein the bit-line extends between the first word-line and the second word-line.
5. The apparatus of claim 1 , wherein:
the memory cell, the bit-line, and the word-line are part of a tile comprising a plurality of memory cells, bit-lines, and word-lines;
the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the bit-line;
the tile has a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the word-line;
the first linear dimension is greater than the second linear dimension; and
the tile comprises a same number of bit-lines and word-lines.
6. The apparatus of claim 1 , wherein the write circuitry comprises a current profile generator to generate a current profile for a set or reset operation of the memory cell.
7. The apparatus of claim 1 , wherein the sensing circuitry comprises a voltage comparator.
8. The apparatus of claim 1 , wherein the memory device is a phase change memory and switch (PCMS) device.
9. A method comprising:
enabling current-limiting circuitry of a selection module to limit a current of as a word-line electrode, the selection module being configured to select a memory cell of a phase change memory (PCM) device;
decoding a bit-line driver and a word-line driver to select a memory cell of the PCM device; and
applying, by write circuitry coupled to the word-line electrode, a current to set or reset a value of the selected memory cell,
wherein:
a potential of the word-line electrode is lower than a potential of a bit-line electrode that is coupled with the memory cell, and
wherein a capacitance of the word-line electrode is lower than a capacitance of the bit-line electrode.
10. The method of claim 9 , wherein enabling the current-limiting circuitry comprises:
applying a voltage to a transistor of the current-limiting circuitry.
11. The method of claim 9 , wherein applying the current comprises applying a current profile having a trapezoid shape to set the value of the selected memory cell or applying a current profile having a rectangular shape to reset the value of the selected memory cell.
12. The method of claim 9 , further comprising:
reading the value of the selected memory cell.
13. The method of claim 12 , wherein reading the value is performed by enabling sensing circuitry coupled to the word-line electrode.
14. The method of claim 13 , wherein:
the sensing circuitry, the current-limiting circuitry, and the write circuitry share a common electrical load of the word-line electrode.
15. A method comprising:
enabling current-limiting circuitry of a selection module to limit a current of a word-line electrode of a phase change memory and switch (PCMS) device, the selection module being configured to select a memory cell of the PCMS device;
decoding a bit-line driver and a word-line driver to select a memory cell of the PCMS device; and
reading, by sensing circuitry coupled to the word-line electrode, a value of the selected memory cell,
wherein:
a potential of the word-line electrode is lower than a potential of a bit-line electrode that is coupled with the memory cell, and
wherein a capacitance of the word-line electrode is lower than a capacitance of the bit-line electrode.
16. The method of claim 15 , wherein the decoding is performed subsequent to enabling the current-limiting circuitry.
17. The method of claim 15 , wherein no bypass operation is performed to bypass the current-limiting circuitry subsequent to enabling the current-limiting circuitry and prior to reading the value of the selected memory cell.
18. An apparatus comprising:
a first memory cell of a three-dimensional array of memory cells;
a bit-line coupled to the first memory cell;
a first word-line coupled to the first memory cell;
a bit-line electrode coupled to the bit-line;
a word-line electrode coupled to the first word-line;
current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module;
sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the memory cell; and
write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell,
wherein the apparatus is configured to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode, and
wherein the first word-line extends in a first dimension of the three-dimensional array and the bit-line extends in a second dimension of the three-dimensional array, the apparatus further comprising:
a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and
a second word-line coupled to the word-line electrode and further coupled to the second memory cell, wherein the bit-line extends between the first word-line and the second word-line.
19. The apparatus of claim 18 , wherein the current-limiting circuitry comprises a current-mirror circuit.
20. An apparatus comprising:
a memory cell of a memory device;
a bit-line coupled to the memory cell;
a word-line coupled to the memory cell;
a bit-line electrode coupled to the bit-line;
a word-line electrode coupled to the word-line;
current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module;
sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the memory cell; and
write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell,
wherein:
the apparatus is configured to provide a potential of the word-line electrode that is lower than a potential of the bit-line electrode,
the memory cell, the bit-line, and the word-line are part of a tile comprising a plurality of memory cells, bit-lines, and word-lines,
the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the bit-line and a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the word-line;
the first linear dimension is greater than the second linear dimension; and
the tile comprises a same number of bit-lines and word-lines.
21. The apparatus of claim 20 , wherein the current-limiting circuitry comprises a transistor gate that is configured to limit a current of the word-line electrode to a maximum current level.