Semiconductor device and fabrication method thereof
The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain.
1. A semiconductor device, comprising:
a semiconductor layer on a substrate;
an isolation layer on the semiconductor layer;
a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and
a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain;
wherein the semiconductor layer and the isolation layer comprise group-III nitride semiconductor material;
wherein a head and tail of the gate are connected through an interconnection line; and
wherein portions of the drain that correspond to connection portions of the gate and the interconnection line employ an arc structure.
2. The semiconductor device according to claim 1 , wherein, respective corners of the gate employ an arc structure, and portions of the source and the drain that correspond to the respective corners also employ an arc structure.
3. The semiconductor device according to claim 1 , wherein, the closed ring structure completely encircles one of the source and the drain.
4. The semiconductor device according to claim 3 , wherein, the other of the source and the drain is located at peripheral of the gate.
5. The semiconductor device according to claim 1 , wherein, tips of the multiple fingers of the source and the drain employ an arc structure, and portions of the gate that correspond to the arc structure of the tips of the multiple fingers also employ an arc structure.
6. The semiconductor device according to claim 1 , further comprising a dielectric layer on the isolation layer between the source and the drain.
7. The semiconductor device according to claim 1 , further comprising a field plate structure and/or a floating gate structure.
8. The semiconductor device according to claim 1 , wherein group-III atom of the group-III nitride semiconductor material comprises Indium, Aluminum, Gallium or combinations thereof.
9. The semiconductor device according to claim 1 , wherein, the gate is connected to a lead pad of the gate via an air bridge across the source or the drain, or is connected to a lead pad of the gate via an interconnection line.
10. The semiconductor device according to claim 1 , wherein, lead pads of the source and the gate are located at one side, and a lead pad of the drain is located at the other side.
11. The semiconductor device according to claim 1 , wherein, width of the multiple fingers of the source and the drain are different.
12. The semiconductor device according to claim 1 , wherein, a corner of the gate is connected to a lead pad of the gate through an interconnection line or an air bridge.
13. A method for fabricating a semiconductor device, comprising steps of:
depositing a semiconductor layer on a substrate;
depositing an isolation layer on the semiconductor layer;
forming a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and
forming a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain;
wherein the semiconductor layer and the isolation layer comprise group-III nitride semiconductor material;
wherein a head and tail of the gate are connected through an interconnection line; and
wherein portions of the drain that correspond to connection portions of the gate and the interconnection line employ an arc structure.
14. The method according to claim 13 , wherein, respective corners of the gate employ an arc structure, and portions of the source and the drain that correspond to the respective corners also employ an arc structure.
15. The method according to claim 13 , wherein, tips of the multiple fingers of the source and the drain are formed as an arc structure, and portions of the gate that correspond to the arc structure of the tips of the multiple fingers are also formed as an arc structure.
16. The method according to claim 13 , wherein, lead pads of the source and the gate are formed at one side, and a lead pad of the drain is formed at the other side.
17. The method according to claim 13 , wherein, the multiple fingers of the source and the drain are formed into different width.
18. The method according to claim 13 , wherein, a corner of the gate is connected to a lead pad of the gate through an interconnection line or an air bridge.
19. A semiconductor device, comprising:
a semiconductor layer on a substrate;
an isolation layer on the semiconductor layer;
a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and
a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain;
wherein the semiconductor layer and the isolation layer comprise group-III nitride semiconductor material; and
wherein width of the multiple fingers of the source and the drain are different.