SRAM cell and method for manufacturing the same

1. A Static Random Access Memory (SRAM) cell, comprising:

a substrate;

a semiconductor layer on the substrate, wherein the semiconductor layer comprises a plurality of stacked semiconductor sub-layers; and

a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate,

wherein the first FinFET comprises a first fin, the first fin being formed of a first number of semiconductor sub-layers of the plurality of stacked semiconductor sub-layers in the semiconductor layer, and the first fin having a first height;

wherein the second FinFET comprises a second fin, the second fin being formed of a second number of semiconductor layers of the plurality of stacked semiconductor sub-layers in the semiconductor layer, and the second fin having a second height, and

wherein a total number of the first number of semiconductor sub-layers and a total number of the second number of semiconductor sub-layers are different from each other, the first fin and the second fin being located on different semiconductor sub-layers with different levels, and the first height of the first fin being different from the second height of the second fin, and

wherein first adjacent semiconductor sub-layers in the first number of the plurality of stacked semiconductor sub-layers in the semiconductor layer comprise different materials, and have etching selectivity with respect to each other, and second adjacent semiconductor sub-layers in the second number of the plurality of stacked semiconductor sub-layers in the semiconductor layer comprise different materials, and have etching selectivity with respect to each other.

2. The SRAM cell according to claim 1 , wherein the first number of the plurality of stacked semiconductor sub-layers of the first fin has a larger thickness than that of a first etching stop sub-layer of the first fin, and wherein the second number of the plurality of stacked semiconductor sub-layers of the second fin has a larger thickness than that of a second etching stop sub-layer of the second fin.

3. The SRAM cell according to claim 2 , wherein the substrate comprises bulk Si, and the etching stop sub-layers comprise SiGe.

4. The SRAM cell according to claim 1 , wherein the substrate comprises a bulk semiconductor substrate.

5. The SRAM cell according to claim 1 , wherein at least one of the first fin and the second fin comprises a block region at a bottom of the at least one of the first fin and the second fin.

6. The SRAM cell according to claim 5 , wherein for a p-type FinFET, the block region comprises n-type dopants, and for an n-type FinFET, the block region comprises p-type dopants.

7. The SRAM cell according to claim 1 , wherein each of the first FinFET and the second FinFET comprises a gate stack crossing over a respective one of the first fin and the second fin,

wherein the gate stack comprises a gate dielectric layer, a work function adjustment layer on the gate dielectric layer, and a gate electrode layer on the work function adjustment layer,

wherein the work function adjustment layer and the gate electrode layer cover respective fin in a whole height of the respective fin, and

wherein the gate electrode layer is separated from the semiconductor layer by an isolation layer.

8. The SRAM cell according to claim 7 , wherein the isolation layer is formed by oxidizing a portion of the semiconductor layer close to a surface of the semiconductor layer.

9. The SRAM cell according to claim 7 , wherein the isolation layer for the first FinFET has a substantially same thickness as the isolation layer for the second FinFET.