IP Library › Granted Patent US 9,252,280
Granted Patent B2
US 9,252,280 · App. 13/510,461 · Granted Feb 2, 2016

MOSFET and method for manufacturing the same

Inventors: Huilong Zhu (Poughkeepsie, NY); Miao Xu (Beijing, CN); Qingqing Liang (Lagrangeville, NY)
Assignee: Institute of Microelectronics, Chinese Academy of Sciences
H01L29/78648H01L29/66742H01L29/78609
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Quick Facts
Patent No.
US 9,252,280
App. No.
13/510,461
Granted
Feb 2, 2016
Kind
B2
Abstract

The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.

Claims (11)

1. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising:

a Semiconductor on Insulator (SOI) wafer, which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer;

a gate stack on the semiconductor layer;

a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and

a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region,

wherein the MOSFET further comprises a back gate located in the semiconductor substrate, the back gate having a first doped region in a lower portion of the back gate with a first doping type, a second doped region in an upper portion of the back gate with the first doping type, and an anti-doped region below the channel region and in the second doped region with a second doping type, wherein the doping concentration of the second doped region of the back gate decreases gradually in a direction from either the source region or the drain region towards the center of the channel region, and wherein the anti-doped region has a doping concentration lower than a doping concentration of the second doped region of the back gate.

2. The MOSFET according to claim 1 , wherein the first doping type of the back gate is the same as or opposite to a doping type of the MOSFET.

3. The MOSFET according to claim 1 , wherein the doping concentration of the back gate is about 1×10 17 cm −3 to about 1×10 20 cm −3 .

4. The MOSFET according to claim 1 , wherein the back gate adjoins the buried insulating layer.

5. The MOSFET according to claim 1 , wherein the second doping type is opposite to the first doping type.

6. The MOSFET according to claim 1 , wherein the doping concentration of the anti-doped region is about 1×10 15 cm −3 to about 1×10 18 cm −3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2012
From: ZHU, HUILONG; XU, MIAO; LIANG, QINGQING
To: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Reel/Frame 028237/0321 →
Priority Claims (1)
CN 2011 1 0274852 · Sep 16, 2011 · national
Continuity (1)
Related Publication 20130099315A1 · Apr 25, 2013