Refresh architecture and algorithm for non-volatile memories
Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
1. A method of refreshing a memory cell array in a non-volatile memory device, the method comprising:
performing a first refresh and second refresh as a function of a system state identifier,
wherein performing the first refresh further comprises:
reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail; and
wherein the performance of the second refresh further comprises:
reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
reading data from a first subset of memory cells;
applying the error correction algorithm to the data read from the first subset of memory cells;
writing the error corrected data into a volatile cache memory; and
wherein the programming comprises copying the error corrected data from the cache memory back into the first subset of memory cells.
2. The method as in claim 1 , further comprising reading data from the memory array out of the memory device against a read reference level, wherein there is a margin between the first refresh reference level and the read reference level, and wherein the second refresh reference level is equal to the read reference level.
3. The method as in claim 1 , wherein the at least one of the first refresh and second refresh are performed repetitively at a frequency which is a function of a temperature of the memory device.
4. The method as in claim 1 , wherein the first refresh is performed upon transition to a system-on state and wherein the second refresh is performed during an active state, the memory device being enabled and accessed by a memory controller unit when in the active state and the system-on state being a transition state, having all system circuits powered, between a power-on state, where system circuits are powering up, and the active state.
5. The method as in claim 1 , further comprising:
receiving a system request to read a data bit out of the memory device while performing the second refresh;
reading the data bit out of the memory array if the data bit address is in a second subset of memory cells different than the first subset of memory cells;
reading the data bit out of the cache memory if the data bit address is in the first subset of memory cells.
6. The method as in claim 5 , wherein the reading of data bit out of the memory array is with a first sense circuit and wherein the reading of the data bit out of the cache memory is with a second sense circuit.
7. The method as in claim 1 , wherein the memory cells comprise phase change memory cells, wherein the volatile cache consists of SRAM cells, wherein the first subset of memory cells consists of a first page of memory cells in a memory partition and wherein the second subset of memory cells consists of a second page of memory cells in the memory partition.
8. A non-volatile memory device, comprising:
an array of memory cells;
a refresh controller configured to perform a first refresh and second refresh as a function of a system state identifier, wherein performing the first refresh further comprises:
reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail;
wherein the performance of the second refresh further comprises:
reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
a cache memory to store data from a first subset of the memory cells read out in response to the refresh controller initiating the second refresh;
an error correction encoding module to error correct the data read from the first subset of memory cells;
a flag bit register to store a flag value in response to an error correction of the data read from the subset of memory cells; and
a multiplexer coupled to the cache memory and the memory array to copy the error corrected data from the cache memory back to the first subset of memory cells in response to the flag value.
9. The non-volatile memory device as in claim 8 , further comprising:
a first sense circuit coupled to the memory array;
a second sense circuit coupled to the cache memory; and
a sense circuit selector coupled to each of the first and second sense circuits and operable to select one of the first and second sense circuits as a function of an address to be read out from the memory device, wherein the second sense circuit is selected in response to the address being within the first subset of memory cells.
10. The non-volatile memory device as in claim 9 , wherein the first sense circuit is selected in response to the address being within a second subset of memory cells in a same memory partition as the first subset of memory cells.
11. The non-volatile memory device as in claim 10 , wherein the memory cells comprise phase change memory cells, wherein the cache memory comprises an SRAM cache, wherein the first subset of memory cells comprises a first page of memory cells, the second subset of memory cells comprises a second page of memory cells, and wherein the error correction encoding module is configured to correct one data bit error in the first page of memory cells.
12. The non-volatile memory device as in claim 8 , wherein the refresh controller is configured to suspend the performance of the second refresh in response to a command received, through a command interface of the memory device, from external to the memory device.
13. The non-volatile memory device as in claim 8 , wherein the non-volatile memory device further comprises:
a refresh timer and a temperature sensor indicative of the memory device temperature coupled to the refresh controller, wherein the refresh controller is configured to perform the first or second refresh at a frequency which is a function of the temperature sensor.
14. A system, comprising:
a memory controller unit;
a non-volatile memory device coupled to the memory controller unit, wherein
the memory device is configured to perform a first refresh and second refresh as a function of the system state identifier, wherein performing the first refresh further comprises:
reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail;
wherein the performance of the second refresh further comprises:
reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
a cache memory to store data from a first subset of the memory cells read out in response to the refresh controller initiating the second refresh;
an error correction encoding module to error correct the data read from the first subset of memory cells;
a flag bit register to store a flag value in response to an error correction of the data read from the subset of memory cells; and
a multiplexer coupled to the cache memory and the memory array to copy the error corrected data from the cache memory back to the first subset of memory cells in response to the flag value.
15. The system as in claim 14 , further comprising a plurality of circuits external to the memory device and the memory controller unit, and wherein the memory device is configured to perform the first refresh in response to the system state identifier indicating that the plurality of external circuits have been powered down.
16. The system as in claim 14 , wherein the memory controller unit is configured to read a refresh status register bit of the memory device prior to accessing the memory array.
17. The system as in claim 16 , wherein the memory controller unit is configured to issue a refresh suspend command to the memory device if the refresh status register bit indicates a memory refresh is occurring, and wherein the memory device is configured to suspend the memory refresh in response to receiving the refresh suspend command from the memory controller unit.
18. The system as in claim 14 , wherein the memory device is further configured to perform the first refresh based on an internal temperature sensor while the memory controller unit is powered down.