Method and apparatus for source-synchronous signaling
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
1. A method for synchronizing a current mode logic (CML) clock signal with a CMOS gate signal, the method comprising:
receiving a CMOS gate signal and a CML clock signal, wherein the CMOS gate signal has an undetermined phase relationship with respect to the CML clock signal; and
retiming the CMOS gate signal based on the CML clock signal so that a transition of the retimed CMOS gate signal is substantially phase-aligned with a midpoint between two adjacent transitions in the CML clock signal.
2. The method of claim 1 , wherein the midpoint between two adjacent transitions of the CML clock signal corresponds to a logic low of the CML clock signal.
3. The method of claim 1 , wherein retiming the CMOS gate signal based on the CML clock signal involves using a transition in the CML clock signal to trigger an enable window in the retimed CMOS gate signal.
4. The method of claim 1 , wherein prior to receiving the CMOS gate signal, the method further comprises synthesizing the CMOS gate signal based on a duration control signal and the CML clock signal, wherein the duration control signal specifies a duration of an enable window in the CMOS gate signal in terms of a number of clock cycles, and wherein a clock period of the CML clock signal determines the shortest duration of the enable window in the CMOS gate signal.
5. The method of claim 1 , wherein prior to gating the CML clock signal using the retimed CMOS gate signal, the method further comprises:
determining a process-voltage-temperature (PVT)-variations-induced phase offset in the retimed CMOS gate signal; and
adjusting the retimed CMOS gate signal to compensate for the determined phase offset.
6. The method of claim 1 , wherein the method further comprises gating the CML clock signal using the retimed CMOS gate signal.
7. An integrated circuit device comprising:
a first circuit to generate a CMOS gate signal;
a second circuit to generate a current mode logic (CML) clock signal; and
a third circuit coupled to both the first circuit and the second circuit, wherein the third circuit is configured to retime the CMOS gate signal based on the CML clock signal so that a transition of the retimed CMOS gate signal is substantially phase-aligned with a midpoint between two adjacent transitions in the CML clock signal.
8. The integrated circuit device of claim 7 , wherein the third circuit is a hybrid CMOS-CML flip-flop, which is further configured to:
receive the CMOS gate signal at a data input;
receive the CML clock signal as a clock input; and
output the retimed CMOS gate signal at a data output.
9. The integrated circuit device of claim 8 , wherein the hybrid CMOS-CML flip-flop is configured with a clock-to-output delay which is substantially equal to one-quarter of a clock period of the CML clock signal, wherein the clock-to-output delay is the time the hybrid CMOS-CML flip-flop takes to propagate a value from the data input to the data output.
10. The integrated circuit device of claim 8 , wherein the hybrid CMOS-CML flip-flop further comprises two cascaded hybrid CMOS-CML latches configured as a master-slave flip-flop.
11. The integrated circuit device of claim 10 , wherein each of the hybrid CMOS-CML latches comprises:
a differential CMOS data input stage which receives the CMOS gate signal; and
a differential CML clock input stage which receives the CML clock signal.
12. The integrated circuit device of claim 7 , further comprising a fourth circuit coupled to both the second circuit and the hybrid CMOS-CML flip-flop, wherein the fourth circuit is configured to gate the CML clock signal using the retimed CMOS gate signal.
13. The integrated circuit device of claim 12 , wherein the fourth circuit is a CML multiplexer.
14. The integrated circuit device of claim 7 , wherein the first circuit further includes:
a receiving module configured to:
receive a duration control signal which specifies a duration of an enable window in the CMOS gate signal in terms of a number of clock cycles; and
receive a CMOS clock signal, wherein a clock period of the CMOS clock signal is substantially equal to a clock period of the CML clock signal; and
a synthesizing module configured to synthesize the CMOS gate signal based on the duration control signal and the CMOS clock signal, wherein the clock period of the CMOS clock signal determines the shortest duration of the enable window in the CMOS gate signal.
15. The integrated circuit device of claim 14 , further comprising a fifth circuit coupled to both the first circuit and the second circuit, wherein the fifth circuit is configured to convert the CML clock signal to the CMOS clock signal.
16. The integrated circuit device of claim 14 , wherein the synthesizing module includes a counter configured to count down an integer value in the duration control signal.
17. The integrated circuit device of claim 7 , wherein the first circuit further includes:
a first logic to determine a process-voltage-temperature (PVT)-variations-induced phase offset in the retimed CMOS gate signal; and
a second logic to generate a delay control signal based on the PVT-variations-induced phase offset.
18. The integrated circuit device of claim 17 , further comprising a sixth circuit coupled to the first circuit, the third circuit, and the fourth circuit, wherein the sixth circuit is configured to:
receive the retimed CMOS gate signal from the third circuit;
receive the delay control signal from the first circuit; and
delay the retimed CMOS gate signal based on the delay control signal to compensate for the PVT-variations-induced phase offset.
19. The integrated circuit device of claim 18 , wherein the sixth circuit comprises a set of serially coupled inverters, wherein each inverter causes a unit delay.
20. The integrated circuit device of claim 7 , wherein the midpoint between two adjacent transitions of the CML clock signal corresponds to a logic low of the CML clock signal.
21. A hybrid CMOS-CML flip-flop, comprising:
a first receiving means to receive a CMOS gate signal at a data input;
a second receiving means to receive a CML clock signal as a clock input;
a retiming means to retime the CMOS gate signal based on the CML clock signal so that a transition of the retimed CMOS gate signal is substantially phase-aligned with a midpoint between two adjacent transitions in the CML clock signal; and
an output means to output the retimed CMOS gate signal at a data output.