IP Library Granted Patent US 9,310,552
Granted Patent B2
US 9,310,552 · App. 13/524,446 · Granted Apr 12, 2016

Methods and apparatus providing thermal isolation of photonic devices

Inventors: Roy Meade (Boise, ID); Gurtej Sandhu (Boise, ID)
Assignee: Micron Technology, Inc.
G02B6/12G02B6/12007G02F1/0147G02F1/3132G02F1/3133G02F2203/15
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Quick Facts
Patent No.
US 9,310,552
App. No.
13/524,446
Granted
Apr 12, 2016
Kind
B2
Abstract

Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.

Claims (31)

1. An integrated structure comprising:

a substrate having an upper surface;

a first trench formed in the upper surface of the substrate;

a device formation region over the upper surface of the substrate;

a first temperature-sensitive photonic device formed in the device formation region;

a waveguide formed in the device formation region and separated from the trench by a portion of the substrate;

a heating device formed in the device formation region for heating the first temperature-sensitive photonic device, wherein the heating device is located over the first trench; and

a first thermal isolation region formed under the heating device, wherein the first thermal isolation region is located in the first trench, such that the first thermal isolation region is provided in the upper surface of the substrate, and wherein the first thermal isolation region reduces dissipation of heat from the heating device into the substrate.

2. The integrated structure of claim 1 , wherein the first trench and first thermal isolation region are formed under the heating device and at least a portion of the first temperature-sensitive photonic device, and wherein the first thermal isolation region is not formed under the wavelength.

3. The integrated structure of claim 1 , wherein the first thermal isolation region comprises a low thermal conductivity material within the first trench.

4. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises an oxide doped with a material having a lower thermal conductivity than the oxide.

5. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises porous silicon dioxide.

6. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises spin-on silicon dioxide.

7. The integrated structure of claim 1 , wherein the heating device is mechanically supported by at least one interconnect extending into the device formation region.

8. The integrated structure of claim 2 , wherein the first trench and first thermal isolation region are formed under the entirety of the first temperature sensitive photonic device.

9. The integrated structure of claim 8 , further comprising a second photonic device formed in the device formation region and wherein the first trench and first thermal isolation region are formed under the second photonic device.

10. The integrated structure of claim 1 , further comprising a second photonic device formed in the device formation region and further comprising a second trench provided in an upper surface of the substrate and a second thermal isolation region under the second photonic device.

11. The integrated structure of claim 2 , wherein the substrate comprises a bulk silicon substrate and the first trench and first thermal isolation region are provided in an upper surface of the silicon.

12. The integrated structure of claim 2 , wherein the substrate comprises a silicon on insulator substrate and the first trench and first thermal isolation region are provided in the insulator of the silicon on insulator substrate.

13. The integrated structure of claim 2 , wherein the first trench and first thermal isolation region form a shallow trench isolation region.

14. The integrated structure of claim 10 , wherein the second thermal isolation region comprises a gap provided in the second trench between the second photonic device and substrate.

15. The integrated structure of claim 3 , wherein the low thermal conductivity material has a thermal conductivity that is less than approximately 0.006 W/cm° C.

16. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises silicon dioxide that has been doped with a dopant having a lower dielectric constant than the silicon dioxide.

17. The integrated structure of claim 16 , wherein the dopant comprises fluorine.

18. The integrated structure of claim 16 , wherein the dopant comprises carbon.

19. The integrated structure of claim 1 , further comprising a second thermal isolation region formed within the first thermal isolation region.

20. The integrated structure of claim 1 , wherein the first temperature-sensitive photonic device comprises a carrier wave modulator.

21. The integrated structure of claim 1 , wherein the first temperature-sensitive photonic device comprises a laser.

22. The integrated structure of claim 19 , wherein the second thermal isolation region has a different thermal conductivity than the first thermal isolation region.

23. The integrated structure of claim 22 , wherein the second thermal isolation region has a lower thermal conductivity than the first thermal isolation region.

24. The integrated structure of claim 19 , wherein the second thermal isolation region comprises a physical gap within the first thermal isolation region.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2012
From: MEADE, ROY; SANDHU, GURTEJ
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028385/0246 →
Continuity (1)
Related Publication 20130336613A1 · Dec 19, 2013