Trench gated power device with multiple trench width and its fabrication process

1. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches have substantially the same depth;

wherein said first and said second trenches each have stepped sides having at least three distinct widths, wherein a top portion of each said trench is wider than a middle portion thereof which has substantially vertical sidewalls, and a bottom portion thereof is narrower than said middle portion;

wherein said first and said second trenches are not identical;

a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding said second trenches.

2. The semiconductor device of claim 1 , wherein said first conductivity type is n-type, and said second conductivity type is p-type.

3. The semiconductor device of claim 1 , wherein said semiconductor mass consists essentially of silicon.

4. The semiconductor device of claim 1 , wherein said gate electrodes are made of doped polysilicon.

5. The semiconductor device of claim 1 , wherein said middle portion of each said trench has a greater vertical extent than said bottom portion thereof, and said bottom portion of each said trench has a greater vertical extent than said top portion thereof

6. The semiconductor device of claim 1 , wherein said gate electrode does not extend into said bottom portion of said first trench, and said field plate electrode does extend into said bottom portion of said second trench.

7. The semiconductor device of claim 1 , wherein doping for said body region is provided by a well diffusion process.

8. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches both extend into a first surface of said semiconductor mass, and all have substantially the same depth;

wherein said first and said second trenches each have stepped sides having at least three distinct widths, wherein a top portion of each said trench is wider than a middle portion thereof which has substantially vertical sidewalls, and a bottom portion thereof is narrower than said middle portion;

wherein said first and said second trenches are not identical;

and wherein said gate electrodes, but not said field plate electrodes, are connected directly to receive a gate drive waveform;

a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and

a first-conductivity-type drain region at a second surface of said semiconductor mass;

whereby, in the ON state, voltage applied to said gate electrode controls majority carrier emission from said source, to thereby allow current conduction between said source and said drain; and whereby said field plate electrodes affect isopotential contours, in the OFF state, to increase the breakdown voltage between said source and said drain.

9. The semiconductor device of claim 8 , wherein said first conductivity type is n-type, and said second conductivity type is p-type.

10. The semiconductor device of claim 8 , wherein said semiconductor mass consists essentially of silicon.

11. The semiconductor device of claim 8 , wherein said gate electrodes are made of doped polysilicon.

12. The semiconductor device of claim 8 , wherein said middle portion of each said trench has a greater vertical extent than said bottom portion thereof, and said bottom portion of each said trench has a greater vertical extent than said top portion thereof

13. The semiconductor device of claim 8 , wherein said gate electrode does not extend into said bottom portion of said first trench, and said field plate electrode does extend into said bottom portion of said second trench.

14. The semiconductor device of claim 8 , wherein doping for said body region is provided by a well diffusion process.

15. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches have substantially the same depth;

wherein said first and said second trenches each have stepped sides having at least three distinct widths, wherein a top portion of each said trench is wider than a middle portion thereof which has substantially vertical sidewalls, and a bottom portion thereof is narrower than said middle portion;

wherein said first and said second trenches are not identical;

a first-conductivity-type source region, in said semiconductor mass, adjacent and self-aligned to said first trenches;

a second-conductivity-type body region adjacent said first trenches;

a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and

modified regions, below and self-aligned to said second trenches, which have a smaller net concentration of second-conductivity-type dopants than said body region does.

16. The semiconductor device of claim 15 , wherein said modified regions are near-intrinsic.

17. The semiconductor device of claim 15 , wherein said modified regions have the same conductivity type as said body region.

18. The semiconductor device of claim 15 , wherein said first conductivity type is n-type, and said second conductivity type is p-type.

19. The semiconductor device of claim 15 , wherein said semiconductor mass consists essentially of silicon.

20. The semiconductor device of claim 15 , wherein said gate electrodes are made of doped polysilicon.