DC-coupled peak detector

1. An apparatus, comprising:

an amplifier configured to amplify a signal;

a peak detector direct-current (DC) coupled to an output of the amplifier, wherein the peak detector includes:

a first comparator stage configured to perform subtraction of a threshold signal from the amplified signal; and

a second comparator stage configured to amplify a differential output signal of the first comparator stage indicative of a result of the subtraction; and

a digital-to-analog converter (DAC) configured to apply an offset compensation signal to an input of the amplifier, wherein the offset compensation signal reduces an offset of a receiver chain that includes the amplifier and the peak detector.

2. The apparatus of claim 1 , further comprising:

a receiver chain including in-phase and quadrature (I and Q) channel paths, wherein the I channel path includes the amplifier and the peak detector, wherein the Q channel path includes another amplifier and another peak detector.

3. The apparatus of claim 2 , wherein a portion of the receiver chain is configured to operate on an input signal within a particular range, wherein a first of the peak detectors is configured to measure the input signal's power relative to an upper boundary of the particular range, and wherein a second of the peak detectors is configured to measure the input signal's power relative to a lower boundary of the particular range.

4. The apparatus of claim 1 , wherein the amplified signal is a differential signal applied to gates of a first transistor and a second transistor within the first comparator stage, wherein the threshold signal is a differential signal applied to gates of a third transistor and a fourth transistor within the first comparator stage, wherein the first and third transistors form a differential pair, and wherein the second and fourth transistors form a differential pair.

5. The apparatus of claim 4 , wherein the first and fourth transistors are coupled to a fifth transistor, wherein the second and third transistors are coupled to a sixth transistor, wherein the first comparator stage is configured to apply a first offset current to a drain of the fifth transistor and a second offset current to a drain of the sixth transistor, and wherein the first comparator stage is further configured to amplify a result of the subtraction.

6. The apparatus of claim 1 , further comprising:

a circuit coupled between the amplifier and the peak detector, wherein the circuit is configured to scale the amplified signal in response to the amplified signal being within a first range.

7. The apparatus of claim 6 , wherein the circuit is further configured to shift the amplified signal in response to the amplified signal being within a second range.

8. The apparatus of claim 1 , wherein the amplifier is a programmable gain amplifier (PGA), wherein the apparatus is configured to:

operate in a first mode in which a gain of the PGA is adjusted based on an output of the peak detector indicating whether the amplified signal is within a boundary of a first range;

operate in a second mode in which the gain of the PGA is adjusted based on an output of the peak detector indicating whether the amplified signal is within a boundary of a second range, and wherein the first range is narrower than the second range.

9. The apparatus of claim 1 , wherein the apparatus is configured to:

measure, for different gain values of the amplifier, an offset for an analog portion of the receiver chain; and

measure an offset between the output of the amplifier and an analog-to-digital converter (ADC) coupled to the output of the amplifier;

wherein the DAC is configured to apply the offset compensation signal based on the measured offsets.

10. A method, comprising:

receiving an amplified signal at a peak detector that is direct-current (DC) coupled to an output of an amplifier;

determining whether to scale or shift the amplified signal responsive to the amplified signal being outside an operating range of the peak detector;

subtracting, at a first comparator stage of the peak detector, a threshold signal from the amplified signal; and

amplifying, at a second comparator stage of the peak detector, a differential output signal of the first comparator stage indicative of a result of the subtracting.

11. The method of claim 10 , wherein the amplified differential output signal is usable to produce an output of the peak detector; and

wherein the method further comprises adjusting a gain of the amplifier based on the output of the peak detector, and wherein the amplifier is an amplifier within an in-phase-channel path of a receiver chain or is an amplifier within a quadrature-channel path of the receiver chain.

12. The method of claim 10 , further comprising:

calibrating a receiver chain that includes the amplifier and the peak detector, wherein the calibrating includes:

for different gain values of the amplifier, measuring an offset for an analog portion of the receiver chain; and

applying an offset compensation signal to an input of the amplifier.

13. The method of claim 12 , wherein the measuring includes shorting of an input of the receiver chain.

14. An apparatus, comprising:

an automatic gain control (AGC) circuit including an amplifier and a peak detector, wherein the peak detector is direct-current (DC) coupled to an output of the amplifier, wherein the amplifier and the peak detector correspond to a path for an in-phase channel of the AGC circuit, and wherein the AGC circuit further includes a path for a quadrature channel; and

wherein the peak detector is configured to use a first comparator stage and a second comparator stage to compare an amplified signal from the amplifier with a threshold signal.

15. The apparatus of claim 14 , further comprising:

a first digital-to-analog converter (DAC) configured to apply a first offset compensation signal to an input of the amplifier; and

a second digital-to-analog converter (DAC) configured to apply a second offset compensation signal to an input of an amplifier in the quadrature-channel path.

16. The apparatus of claim 15 , wherein the apparatus is configured to:

calculate a first rounding error indicative of a difference between the first offset compensation signal applied by the first DAC and an ideal offset compensation signal to reduce an offset of the in-phase channel path;

calculate a second rounding error indicative of a difference between the second offset compensation signal applied by the second DAC and an ideal offset compensation signal to reduce an offset of the quadrature channel path; and

adjusting one of the first and second offset compensation signals in response to the first and second rounding errors differing by more than a threshold.

17. The apparatus of claim 14 , wherein the first comparator stage is configured to perform subtraction of the threshold signal from the amplified signal, and wherein the second comparator stage is configured to amplify a differential output signal of the first comparator stage indicative of a result of the subtraction.

18. A method, comprising:

amplifying a signal in an automatic gain control (AGC) circuit including an amplifier and a peak detector, wherein the peak detector is direct-current (DC) coupled to an output of the amplifier, wherein the amplifier and the peak detector correspond to a path for an in-phase channel of the AGC circuit, and wherein the AGC circuit further includes a path for a quadrature channel; and

using a first comparator stage and a second comparator stage of the peak detector to compare the amplified signal with a threshold signal.

19. The method of claim 18 , further comprising:

applying, by a first digital-to-analog converter (DAC), a first offset compensation signal to an input of the amplifier; and

applying, by a second digital-to-analog converter (DAC), a second offset compensation signal to an input of an amplifier in the quadrature-channel path.

20. The method of claim 19 , further comprising:

calculating a first rounding error indicative of a difference between the first offset compensation signal applied by the first DAC and an ideal offset compensation signal to reduce an offset of the in-phase channel path;

calculating a second rounding error indicative of a difference between the second offset compensation signal applied by the second DAC and an ideal offset compensation signal to reduce an offset of the quadrature channel path; and

adjusting one of the first and second offset compensation signals in response to the first and second rounding errors differing by more than a threshold.

21. The method of claim 18 , wherein the using includes:

performing, at the first comparator stage, a subtraction of the threshold signal from the amplified signal; and

amplifying, at the second comparator stage, a differential output signal of the first comparator stage indicative of a result of the subtraction.