System and method for soft error detection in memory devices
View Patent ↗A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.
1. A system for detecting a soft error in a memory device during a memory read/write operation, comprising:
a latch having a clock input terminal for receiving a first clock signal and a data input terminal for receiving input data corresponding to the memory read/write operation, wherein the latch latches the input data at the beginning of the memory read/write operation in response to a rising edge of the first clock signal and generates a latch output;
a master flip-flop having a clock input terminal for receiving a second clock signal and a data input terminal connected to the latch for receiving the latch output, wherein the master flip-flop continuously receives and stores the latch output during the memory read/write operation based on the second clock signal;
a slave flip-flop having a clock input terminal for receiving the second clock signal and an input terminal connected to an output of the master flip-flop for receiving the latch output, wherein the slave flip-flop receives and stores the latch output at the end of memory read/write operation based on the second clock signal; and
a comparator, having a first input that receives the input data and a second input connected to an output of the slave flip-flop for receiving the latch output therefrom, for comparing the input data and the latch output and thereby detecting a soft error during the memory read/write operation.
2. The system of claim 1 , wherein the first and second clock signals are synchronized.
3. The system of claim 1 , wherein the master flip-flop includes a first switch that receives the second clock signal for and enables the master flip-flop at a rising edge of the second clock signal and disables the master flip-flop at a falling edge of the second clock signal.
4. The system of claim 3 , wherein the slave flip-flop includes a second switch that receives the second clock signal and enables the slave flip-flop at the falling edge of the second clock signal and disables the slave flip-flop at the rising edge of the second clock signal.
5. The system of claim 1 , wherein the master and slave flip-flops comprise scan flip-flops and are part of a scan chain circuit of the memory device.
6. The system of claim 1 , wherein the latch comprises at least one of an address latch and a control latch.
7. The system of claim 1 , wherein the input data includes at least one of address and control signal values corresponding to the memory read/write operation.
8. The system of claim 1 , wherein the memory device comprises at least one of a random access memory (RAM), read only memory (ROM), dynamic-RAM (DRAM), static-RAM (SRAM), and flash memory.
9. A memory device, comprising:
a plurality of latches comprising address and control latches, wherein the address and control latches receive corresponding address and control signals corresponding to a memory read/write operation, at respective input terminals and a first clock signal at respective clock terminals, latch the address and control signals at the beginning of the memory read/write operation in response to a rising edge of the first clock signal and generate latch outputs;
a plurality of master flip-flops corresponding to the plurality of latches, wherein each master flip-flop has a clock input terminal for receiving a second clock signal and an input terminal connected to an output of a corresponding latch for receiving the latch output, wherein the master flip-flop continuously receives and stores the latch output during the memory read/write operation based on the second clock signal;
a plurality of slave flip-flops connected to corresponding plurality of master flip-flops, wherein each slave flip-flop has a clock input terminal for receiving the second clock signal and an input terminal connected to an output of a corresponding master flip-flop for receiving the latch output, wherein the slave flip-flop receives and stores the latch output at the end of a memory read/write operation based on the second clock signal; and
a comparator having first inputs that receive the address and control signals and second inputs connected to outputs of the plurality of slave flip-flops for receiving the latch outputs therefrom and comparing the latch outputs with the address and control signals to detect soft errors during the memory read/write operation.
10. The memory device of claim 9 , wherein the first and second clock signals are synchronized.
11. The memory device of claim 9 , wherein each master flip-flop includes a first switch that receives the second clock signal and enables the master flip-flop at a rising edge of the second clock signal and disables the master flip-flop at a falling edge of the second clock signal.
12. The memory device of claim 11 , wherein each slave flip-flop includes a second switch that receives the second clock signal and enables the slave flip-flop at the falling edge of the second clock signal and disables the slave flip-flop at the rising edge of the second clock signal.
13. The memory device of claim 9 , wherein the master and slave flip-flops comprise scan flip-flops and are part of a scan chain circuit of the memory device.
14. The memory device of claim 9 , wherein the memory device comprises at least one of a random access memory (RAM), read only memory (ROM), dynamic-RAM (DRAM), static-RAM (SRAM), and flash memory.
15. A method for detecting a soft error during a memory read/write operation in a memory device, comprising:
receiving input data corresponding to the memory read/write operation by a latch at the beginning of the memory read/write operation, in response to a rising edge of a first clock signal, wherein the latch latches the input data and generates a latch output;
continuously receiving the latch output at a master flip-flop during the memory read/write operation, based on a second clock signal, wherein the master flip-flop stores the latch output;
receiving the latch output at a slave flip-flop from the master flip-flop, at the end of the memory read/write operation, based on the second clock signal, wherein the slave flip-flop stores the latch output; and
comparing the latch output with the input data by a comparator, to detect the soft error during the memory read/write operation.
16. The method of claim 15 , wherein the first and second clock signals are synchronized.
17. The method of claim 15 , further comprising enabling the master flip-flop at a rising edge of the second clock signal and disabling the master flip-flop at a falling edge of the second clock signal.
18. The method of claim 17 , further comprising enabling the slave flip-flop at the falling edge of the second clock signal and disabling the slave flip-flop at the rising edge of the second clock signal.
19. The method of claim 15 , wherein the input data includes at least one of address and control signal values corresponding to the memory read/write operation.