IP Library › Granted Patent US 8,748,886
Granted Patent B2
US 8,748,886 · App. 13/533,121 · Granted Jun 10, 2014

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Satoshi Shinohara (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,748,886
App. No.
13/533,121
Granted
Jun 10, 2014
Kind
B2
Abstract

A transistor which is formed using an oxide semiconductor layer and has electric characteristics needed for the intended use, and a semiconductor device including the transistor are provided. The transistor is formed using an oxide semiconductor stack including at least a first oxide semiconductor layer in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which is provided over the first oxide semiconductor layer and has an energy gap different from that of the first oxide semiconductor layer. There is no limitation on the stacking order of the first oxide semiconductor layer and the second oxide semiconductor layer as long as their energy gaps are different from each other.

Claims (82)

1. A semiconductor device comprising:

a substrate having an insulating surface;

a source electrode layer and a drain electrode layer over the substrate;

a first oxide semiconductor layer over the source electrode layer and the drain electrode layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a gate insulating layer over the second oxide semiconductor layer; and

a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises a stack of a first oxide semiconductor film and a second oxide semiconductor film,

wherein the first oxide semiconductor film and the second oxide semiconductor film each include crystals,

wherein an energy gap of the first oxide semiconductor film is different from an energy gap of the second oxide semiconductor film, and

wherein the second oxide semiconductor layer covers and is in contact with side surfaces of the first oxide semiconductor film and side surfaces of the second oxide semiconductor film.

2. The semiconductor device according to claim 1 ,

wherein the energy gap of the first oxide semiconductor film is larger than or equal to 3 eV, and

wherein the energy gap of the second oxide semiconductor film is smaller than 3 eV.

3. The semiconductor device according to claim 1 , wherein the first and second oxide semiconductor layers includes an impurity region, and wherein the impurity region does not overlap with the gate electrode layer.

4. The semiconductor device according to claim 1 , wherein c-axes of crystals are aligned in a direction perpendicular to a surface of the first and second oxide semiconductor layers.

5. A semiconductor device comprising:

a substrate having an insulating surface;

a source electrode layer and a drain electrode layer formed over the substrate;

a first oxide semiconductor layer over the source electrode layer and the drain electrode layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a gate insulating layer over the second oxide semiconductor layer; and

a gate electrode layer overlapping with the second oxide semiconductor layer with the gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises a stack of a first oxide semiconductor film and a second oxide semiconductor film,

wherein an energy gap of the first oxide semiconductor film is different from an energy gap of the second oxide semiconductor film, and

wherein the second oxide semiconductor layer covers and is in contact with side surfaces of the first oxide semiconductor film and side surfaces of the second oxide semiconductor film.

6. The semiconductor device according to claim 5 ,

wherein the energy gap of the first oxide semiconductor film is larger than or equal to 3 eV, and

wherein the energy gap of the second oxide semiconductor film is smaller than 3 eV.

7. The semiconductor device according to claim 5 ,

wherein the second oxide semiconductor layer comprises a third oxide semiconductor film, and

wherein an energy gap of the third oxide semiconductor film is equal to the energy gap of the first oxide semiconductor film.

8. The semiconductor device according to claim 7 ,

wherein the second oxide semiconductor film is interposed between the first oxide semiconductor film and the third oxide semiconductor film.

9. The semiconductor device according to claim 5 ,

wherein the second oxide semiconductor layer includes an impurity region, and

wherein the impurity region does not overlap with the gate electrode layer.

10. The semiconductor device according to claim 5 ,

wherein the first oxide semiconductor layer includes crystals, and

wherein c-axes of the crystals are aligned in a direction perpendicular to a surface of the first oxide semiconductor layer.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming a source electrode layer and a drain electrode layer over an oxide insulating film;

forming a first oxide semiconductor layer over the source electrode layer and the drain electrode layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer;

forming a gate insulating layer over the source electrode layer, the drain electrode layer, and the second oxide semiconductor layer; and

forming a gate electrode layer overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer with the gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises a stack of a first oxide semiconductor film and a second oxide semiconductor film,

wherein the first oxide semiconductor film and the second oxide semiconductor film each include crystals,

wherein an energy gap of the first oxide semiconductor film is different from an energy gap of the second oxide semiconductor film, and

wherein the second oxide semiconductor layer is in contact with side surfaces of the first oxide semiconductor film and side surfaces of the second oxide semiconductor film.

12. The method for manufacturing a semiconductor device according to claim 11 , further comprising a step of introducing oxygen into the second oxide semiconductor layer from above the gate insulating layer after the gate insulating layer is formed.

13. The method for manufacturing a semiconductor device according to claim 11 , further comprising a step of introducing a dopant into the first oxide semiconductor layer and the second oxide semiconductor layer with use of the gate electrode layer as a mask after the gate electrode layer is formed.

14. The semiconductor device according to claim 5 ,

wherein the side surfaces of the first oxide semiconductor film are outer side surfaces, and

wherein the side surfaces of the second oxide semiconductor film are outer side surfaces.

15. The method for manufacturing a semiconductor device according to claim 11 , wherein c-axes of crystals are aligned in a direction perpendicular to a surface of the first and second oxide semiconductor layers.

16. A semiconductor device comprising:

a substrate;

a first oxide semiconductor film over the substrate;

a second oxide semiconductor film over the first oxide semiconductor film;

a third oxide semiconductor film over the second oxide semiconductor film;

a gate insulating layer over the third oxide semiconductor film; and

a gate electrode layer overlapping with at least the second oxide semiconductor film with the gate insulating layer interposed therebetween,

wherein an energy gap of the first oxide semiconductor film is different from an energy gap of the second oxide semiconductor film, and

wherein the third oxide semiconductor film covers and is in contact with side surfaces of the first oxide semiconductor film and side surfaces of the second oxide semiconductor film.

17. The semiconductor device according to claim 16 ,

wherein the energy gap of the first oxide semiconductor film is larger than or equal to 3 eV, and

wherein the energy gap of the second oxide semiconductor film is smaller than 3 eV.

18. The semiconductor device according to claim 16 ,

wherein an energy gap of the third oxide semiconductor film is equal to the energy gap of the first oxide semiconductor film.

19. The semiconductor device according to claim 16 ,

wherein the third oxide semiconductor film includes an impurity region, and

wherein the impurity region does not overlap with the gate electrode layer.

20. The semiconductor device according to claim 16 ,

wherein the first oxide semiconductor film, the second oxide semiconductor film and the third oxide semiconductor film each include crystals, and

wherein c-axes of the crystals are aligned in a direction perpendicular to a surface of the second oxide semiconductor film.

21. A method for manufacturing a semiconductor device, comprising the steps of: forming a first oxide semiconductor layer and a second oxide semiconductor layer over a substrate, wherein the second oxide semiconductor layer is provided over the first oxide semiconductor layer; forming an oxide semiconductor film over the second oxide semiconductor layer so as to cover and be in contact with side surfaces of the first oxide semiconductor layer and side surfaces of the second oxide semiconductor layer; processing the oxide semiconductor film to form a third oxide semiconductor layer which covers and is in contact with the side surfaces of the first oxide semiconductor layer and the side surfaces of the second oxide semiconductor layer; forming a gate insulating layer over the third oxide semiconductor layer; and forming a gate electrode layer overlapping with at least the second oxide semiconductor layer with the gate insulating layer interposed therebetween, and wherein an energy gap of the first oxide semiconductor layer is different from an energy gap of the second oxide semiconductor layer.

22. The method for manufacturing a semiconductor device according to claim 21 , further comprising a step of introducing oxygen into the third oxide semiconductor layer from above the gate insulating layer after the gate insulating layer is formed.

23. The method for manufacturing a semiconductor device according to claim 21 , further comprising a step of introducing a dopant into the third oxide semiconductor layer with use of the gate electrode layer as a mask after the gate electrode layer is formed.

24. The method for manufacturing a semiconductor device according to claim 21 ,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each include crystals, and

wherein c-axes of the crystals are aligned in a direction perpendicular to a surface of the second oxide semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: YAMAZAKI, SHUNPEI; SHINOHARA, SATOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 028443/0391 →
Priority Claims (1)
JP 2011-152190 · Jul 8, 2011 · national
Continuity (1)
Related Publication 20130009220A1 · Jan 10, 2013