Method of manufacturing semiconductor device

1. A method of manufacturing a semiconductor device, comprising:

(a) forming a processing target;

(b) forming a first supporter on said processing target;

(c) forming a first mask so as to contact one side surface of said first mask with a side surface of said first supporter;

(d) patterning said processing target using, as masks, said first mask and said first supporter;

(e) forming a second supporter so as to be contacted with a side surface of said processing target that is exposed in the (d) and the other side surface of said first mask;

(f) removing said first supporter; and

(g) patterning said processing target using, as masks, said first mask and said second supporter.

2. The method according to claim 1 , wherein

in the (c), two masks are formed on both side surfaces of said first supporter as said first mask.

3. The method according to claim 1 , wherein

in the (c), said first mask is formed as a sidewall on said first supporter.

4. The method according to claim 1 , further comprising:

forming a third supporter that supports at least one side surface of said processing target after the (g).

5. The method according to claim 1 , wherein

in at least any one of the (d) and the (g), said processing target is removed from an exposed surface of said processing target to an undersurface thereof.

6. The method according to claim 1 , wherein

in at least any one of the (d) and the (g), an upper part of said processing target in the exposed surface is partially removed so as to leave a lower part of the processing target.

7. The method according to claim 1 , further comprising:

(h) processing said processing target into a line shape extending in a first direction before the (c); wherein

in the (c), said first mask and said first supporter are processed into a line shape extending in a second direction that intersects said first direction.

8. The method according to claim 7 , further comprising:

forming a fourth supporter extending in said first direction before the (h); wherein

in the (h), said processing target is formed as a sidewall on said fourth supporter.

9. The method according to claim 7 , wherein

said first direction and said second direction intersect each other at right angles.

10. The method according to claim 1 , further comprising:

(i) forming a second mask on the other surface of said first mask after the (d); and

(j) processing said processing target using, as masks, said first mask, said first supporter and said second mask; wherein

in the (d), an upper part of said processing target in a first exposed surface is partially removed to form a first recess in said first exposed surface of said processing target;

in the (i), said second mask is formed so as to cover a part of a bottom of said first recess and to expose the remaining part of said bottom of said first recess; and

in the (j), said remaining part of said processing target in said first recess is removed.

11. The method according to claim 10 , further comprising:

(k) forming a fifth supporter in a region where said processing target is removed in the (j);

(l) removing said first supporter so as to expose said processing target;

(m) removing a part of an upper part of said processing target in a second exposed surface so as to form a second recess in said second exposed surface of said processing target that is exposed in the (l);

(n) forming a third mask on said one side surface of said first mask so as to cover a part of a bottom of said second recess and to expose the remaining part of said bottom of said second recess; and

(o) removing said remaining part of said second recess of said processing target, using masks of said third mask, said first mask, said second mask and said fifth supporter.

12. The method according to claim 11 , wherein

at least in the (i), said second mask is formed as a sidewall on a side surface of said first recess and said processing target and, in the (n), said third mask is formed as a sidewall on a side surface of said second recess of said first mask and said processing target.

13. The method according to claim 11 , further comprising:

forming a sixth supporter in a region where said processing target is removed in the (o).

14. The method according to claim 1 , wherein

said first supporter comprises silicon oxide;

said first mask comprises tungsten; and

said second supporter comprises silicon nitride.

15. The method according to claim 1 , further comprising:

(p) removing said first mask so as to expose said processing target after processing said processing target.

16. The method according to claim 15 , further comprising:

removing an element disposed around said processing target partially so as to make flush with a top surface of said processing target exposed in the (p).

17. The method according to claim 15 , further comprising:

(q) forming a phase change material that is electrically connected with an exposed top surface of said processing target after the (p); and

(r) forming a conductor that is electrically connected with said phase change material on said phase change material; wherein

a material of said processing target comprises a conductor.

18. The method according to claim 17 , further comprising:

(s) removing a part of said processing target exposed in the (p); wherein

in the (q), said phase change material is formed in a region where said processing target is removed in the (s).

19. The method according to claim 1 , further comprising:

(t) forming an electrode pad before the (a); wherein

said processing target comprises a conductor; and

in the (a), said processing target is formed so as to be electrically connected with said electrode pad.

20. The method according to claim 19 , wherein

in the (t), a plurality of said electrode pads are formed so as to be interspersed in a gridlike fashion; and

after the (a), said processing target is processed into a line shape extending along a line of said electrode pads arranged along a first direction.