On-chip capacitors with a variable capacitance for a radiofrequency integrated circuit

1. A method of fabricating an on-chip capacitor having a variable capacitance, the method comprising:

forming first and second ports in a dielectric layer that are configured to be powered with opposite polarities and that have a parallel arrangement;

forming a first and second electrodes in the dielectric layer with a parallel arrangement in a space between the first and second ports and aligned transverse to the first and second ports, wherein the first electrode has an end separated from the first port by a first gap so that the first port and the end of the first electrode lack direct physical connection, and the second electrode has an end separated from the second port by a second gap so that the second port and the end of the second electrode lack direct physical connection;

forming a first voltage-controlled unit configured to selectively open and close a first current path coupling the first electrode with the first port; and

forming a second voltage-controlled unit configured to selectively open and close a second current path coupling with the second port;

wherein the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port than when the first and second electrodes are electrically isolated from the first and second ports.

2. The method of claim 1 wherein the on-chip capacitor is carried by a back-end-of-line (BEOL) wiring structure on a chip, and further comprising:

fabricating an integrated circuit on the chip that is electrically coupled with the first and second ports.

3. The method of claim 2 wherein the first and second voltage-controlled units are first and second field effect transistors of the integrated circuit fabricated on the chip.

4. The method of claim 3 wherein forming the first and second voltage-controlled units further comprises:

fabricating the first and second field effect transistors on the chip; and

forming conductive features configured to concurrently supply a control voltage to a first gate stack of the first field effect transistor and to a second gate stack of the second field effect transistor to simultaneously couple the first electrode with the first port and the second electrode with the second port and provide the larger capacitance value.

5. The method of claim 2 wherein the on-chip capacitor is configured to be switched by the first and second voltage-controlled units while the integrated circuit is operating.

6. A method of fabricating an on-chip capacitor having a variable capacitance, the method comprising:

forming first and second ports in a dielectric layer that are configured to be powered with opposite polarities;

forming first and second electrodes in the dielectric layer;

forming a first voltage-controlled unit configured to selectively couple the first electrode with the first port; and

forming a second voltage-controlled unit configured to selectively couple the second electrode with the second port;

forming a third electrode in the dielectric layer that is directly connected with the first port; and

forming a fourth electrode in the dielectric layer that is directly connected with the second port,

wherein the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port than when the first and second electrodes are electrically isolated from the first and second ports, the third and fourth electrodes provide a fixed capacitance that is increased when the first and second voltage-controlled units are in the second state, the on-chip capacitor is integrated into one or more metallization levels of a back-end-of-line (BEOL) wiring structure, and the third and fourth electrodes are formed in a different metallization level than the first and second electrodes.

7. The method of claim 6 wherein the first, second, third, and fourth electrodes are formed with a juxtaposed arrangement, and the first electrode is separated from the second electrode by the third and fourth electrodes.

8. The method of claim 7 wherein the first and second electrodes are formed with a symmetrical arrangement on opposite sides of the third and fourth electrodes.

9. A method of fabricating an on-chip capacitor having a variable capacitance, the method comprising:

forming first and second ports in a dielectric layer that are configured to be powered with opposite polarities;

forming first and second electrodes in the dielectric layer, wherein the first and second electrodes are disposed in a first metallization level of a multi-level back-end-of-line (BEOL) wiring structure;

forming third and fourth electrodes disposed in a second metallization level different than the first metallization level;

forming a first voltage-controlled unit configured to selectively couple the first electrode with the first port; and

forming a second voltage-controlled unit configured to selectively couple the second electrode with the second port;

wherein the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port than when the first and second electrodes are electrically isolated from the first and second ports.

10. The method of claim 9 wherein the third electrode is directly connected with the first port, the fourth electrode is directly connected with the second port, and the third and fourth electrodes provide a fixed capacitance that is increased to provide the larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port.

11. The method of claim 9 wherein forming the third and fourth electrodes further comprises:

forming the third electrode with a lateral position in the second metallization level such that the third electrode is aligned vertically with the first electrode; and

forming the fourth electrode with a lateral position in the second metallization level such that the fourth electrode is aligned vertically with the second electrode.

12. The method of claim 11 further comprising:

forming a first plurality of metal-filled vias extending between the first electrode and the third electrode so that the first and third electrodes are shorted together; and

forming a second plurality of metal-filled vias extending between the second electrode and the fourth electrode so that the second and fourth electrodes are shorted together.

13. The method of claim 9 wherein forming the first and second ports further comprises:

forming the first and second ports with a spaced-apart, substantially parallel arrangement.

14. The method of claim 13 wherein forming the first and second electrodes further comprises:

forming the first and second electrodes between the first and second ports at an orientation that is approximately orthogonal relative to the first and second ports.