Body-contacted partially depleted silicon on insulator transistor

1. A circuit comprising:

a switch transistor having gate, source, drain, and body contacts;

first and second resistors coupled in series with one another and further coupled with and between the source and drain contacts; and

a discharge transistor having a first contact coupled with the body contact of the switch transistor, a second contact coupled with the gate contact of the switch transistor, and a gate contact coupled with the first and second resistors.

2. The circuit of claim 1 , wherein the gate contact is coupled with a first node between the first and second resistors.

3. The circuit of claim 1 , wherein the first node is a virtual ground.

4. The circuit of claim 1 , wherein the circuit is a silicon on insulator (SOI) device.

5. The circuit of claim 4 , wherein the SOI device comprises a partially depleted SOI device.

6. The circuit of claim 1 , wherein the circuit is an n-channel metal oxide semiconductor field effect transistor (NMOS) switch configured to transmit a negative DC voltage.

7. The circuit of claim 1 , wherein the circuit is a p-channel metal oxide semiconductor field effect transistor (PMOS) switch configured to transmit a positive DC voltage.

8. The circuit of claim 1 , wherein the first resistor and the second resistor are of equal size.

9. The circuit of claim 1 , wherein the first contact of the discharge transistor is a source contact of the discharge transistor and the second contact of the discharge transistor is a drain contact of the discharge transistor.

10. The circuit of claim 1 , wherein the circuit comprises a common-gate amplifier.

11. A partially-depleted silicon on insulator (PDSOI) device comprising:

a first transistor configured to pass a signal when turned on and to prevent passage of the signal when turned off;

a node configured to provide a virtual ground; and

a second transistor having a first contact coupled with the node and a second contact coupled with a body of the first transistor to provide a discharge path to the body when the first transistor is turned off.

12. The PDSOI device of claim 11 , wherein the first contact is a gate contact and the second contact is a source contact.

13. The PDSOI device of claim 11 , further comprising:

a first resistor and a second resistor coupled in series with one another,

wherein the node is disposed between the first and second resistors.

14. The PDSOI device of claim 11 , wherein the first transistor comprises a source contact coupled with the first resistor and a drain contact coupled with the second resistor.

15. The PDSOI device of claim 11 , wherein the second transistor is configured to be turned off when the first transistor is turned on.

16. The PDSOI device of claim 15 , wherein the second transistor is further configured to be turned on when the first transistor is turned off.

17. A system comprising:

a transceiver configured to provide a signal;

a power amplification module configured to receive the signal from the transceiver and amplify the signal for transmission; and

a switch circuit, disposed in the transceiver or in the PA module, the switch circuit including a partially-depleted, silicon on insulator (PDSOI) device having:

a switch transistor configured to switch the signal;

a pair of resistors configured to provide a virtual ground at a first node; and

a discharge transistor coupled with the switch transistor and the first node and configured to provide a discharge path to discharge charges in a body of the switch transistor.

18. The system of claim 17 , wherein the discharge transistor is configured to provide the discharge path when the switch transistor is turned off.

19. The system of claim 17 , wherein the signal is to be transmitted with a power of 32 dBM or greater and having a frequency of 1800 megahertz or higher.

20. The system of claim 17 , wherein the signal is to be transmitted with a power of 34 dBM or greater and having a frequency within 800-915 megahertz.