Package with metal-insulator-metal capacitor and method of manufacturing the same

1. A package comprising:

a chip in a first area of the package, the chip comprising a contact at a top surface of the chip;

a molding compound in a second area of the package adjacent to the first area, wherein a bottom surface of the chip is level with a bottom surface of the molding compound and the top surface of the chip is level with a top surface of the molding compound;

a first polymer layer on the chip, the contact, and the molding compound;

a second polymer layer on the first polymer layer;

a plurality of interconnect structures between the first polymer layer and the second polymer layer;

a metal-insulator-metal (MIM) capacitor on the second polymer layer and electrically coupled to a first interconnect structure of the plurality of interconnect structures, wherein the MIM capacitor comprises a lower metal layer extending over an upper surface of the second polymer layer and extending along a sidewall of the second polymer layer, wherein the MIM capacitor further comprises a capacitor dielectric layer overlying the lower metal layer and extending along a sidewall of the lower metal layer, and wherein the MIM capacitor further comprises an upper metal layer overlying the capacitor dielectric layer;

a conductive structure extending continuously from contact with the MIM capacitor to contact with a second interconnect structure of the plurality of interconnect structures, wherein the conductive structure covers the MIM capacitor, wherein the conductive structure further contacts sidewalls respectively of the capacitor dielectric layer and the second polymer layer, and wherein the conductive structure contacts a sidewall of the upper metal layer and contacts top surfaces respectively of the second polymer layer and the second interconnect structure;

a metal bump over and electrically coupled to a third interconnect structure of the plurality of interconnect structures, wherein a bottom surface of the metal bump is spaced between a top surface of the MIM capacitor and a bottom surface of the MIM capacitor; and

an isolation coating completely covering the MIM capacitor and the conductive structure, and further contacting the second polymer layer, wherein the isolation coating comprises an opening, and wherein the metal bump is in the opening and laterally spaced from sidewalls of the opening.

2. The package of claim 1 , the capacitor dielectric layer comprises a nitride layer conformally overlying the lower metal layer.

3. The package of claim 2 , wherein the lower metal layer comprises at least one of a titanium layer or a titanium nitride layer.

4. The package of claim 2 , wherein the upper metal layer comprises at least one of a titanium layer or a titanium nitride layer.

5. The package of claim 1 , wherein the conductive structure comprises at least one of copper, copper alloy, titanium, or titanium nitride.

6. The package of claim 1 , wherein the plurality of interconnect structures comprises copper.

7. The package of claim 1 , wherein the molding compound is free from enclosing a conductive element.

8. The package of claim 1 , wherein the conductive structure comprises a first barrier layer and a first under-bump metallization (UBM) structure, wherein the first barrier layer covers and contacts the MIM capacitor, where the first UBM structure covers and contacts the first barrier layer, and wherein the package further comprises:

a second barrier layer over and contacting the third interconnect structure of the plurality of interconnect structures; and

a second UBM structure covering and contacting the second barrier layer, wherein the metal bump is over and contacts the second UBM structure, and wherein bottom surfaces respectively of the first and second UBM structures are vertically offset.

9. A package comprising:

a chip in a first area of the package, the chip comprising a contact at a top surface of the chip;

a molding compound in a second area of the package adjacent to the first area, wherein a bottom surface of the chip is level with a bottom surface of the molding compound and the top surface of the chip is level with a top surface of the molding compound;

a first polymer layer on the chip, the contact, and the molding compound;

a second polymer layer on the first polymer layer;

a plurality of interconnect structures between the first polymer layer and the second polymer layer;

a metal-insulator-metal (MIM) capacitor on the second polymer layer and electrically coupled to a first interconnect structure of the plurality of interconnect structures, wherein the MIM capacitor comprises a lower metal layer, a capacitor dielectric layer overlying the lower metal layer and extending along a sidewall of the lower metal layer, and an upper metal layer overlying the capacitor dielectric layer;

an under-bump metallization (UBM) layer comprising a first UBM segment covering the MIM capacitor, and further comprising a second UBM segment laterally spaced from the first UBM segment, wherein a top surface of the first UBM segment is elevated relative to a top surface of the second UBM segment;

a first barrier structure between and contacting the first UBM segment and the MIM capacitor, wherein the first barrier structure covers the MIM capacitor and contacts a sidewall of the capacitor dielectric layer; and

an isolation coating covering the MIM capacitor and the first UBM segment, wherein the isolation coating comprises an opening exposing the second UBM segment, and wherein the second UBM segment is spaced from sidewalls of the opening.

10. The package of claim 9 , wherein the MIM capacitor is over the chip in the first area.

11. The package of claim 9 , wherein the capacitor dielectric layer comprises a nitride layer conformally overlying the lower metal layer.

12. The package of claim 11 , wherein at least one of the lower metal layer and the upper metal layer comprises at least one of a titanium layer, a titanium nitride layer, or a copper layer.

13. The package of claim 9 , wherein the interconnect structures comprise copper.

14. The package of claim 9 , wherein the molding compound is free from enclosing a conductive element.

15. The package of claim 9 ,

wherein the first barrier structure has the same width as the first UBM segment.

16. The package of claim 9 , further comprising:

a metal bump over and electrically coupled to a second interconnect structure of the plurality of interconnect structures through the second UBM segment, wherein the metal bump is in the opening and spaced from the sidewalls of the opening.

17. A package comprising:

a chip in a first area of the package, the chip comprising a contact at a top surface of the chip;

a molding compound in a second area of the package adjacent to the first area, wherein a bottom surface of the chip is level with a bottom surface of the molding compound and the top surface of the chip is level with a top surface of the molding compound;

a first polymer layer on the chip, the contact, and the molding compound;

a second polymer layer on the first polymer layer,

a plurality of interconnect structures between the first polymer layer and the second polymer layer;

a metal-insulator-metal (MIM) capacitor on the second polymer layer and electrically coupled to a first interconnect structure of the plurality of interconnect structures, wherein the MIM capacitor comprises a lower metal layer, a capacitor dielectric layer overlying the lower metal layer and extending along a sidewall of the lower metal layer, and an upper metal layer overlying the capacitor dielectric layer;

an under-bump metallization (UBM) layer comprising a first UBM segment covering the MIM capacitor, and further comprising a second UBM segment laterally spaced from the first UBM segment, wherein a top surface of the first UBM segment is elevated relative to a top surface of the second UBM segment, and wherein the first UBM segment extends continuously from over the MIM capacitor to over a second interconnect structure of the plurality of interconnect structures; and

a barrier layer between and contacting the UBM layer and the MIM capacitor, wherein the barrier layer extends continuously from direct contact with the MIM capacitor to direct contact with the second interconnect structure, wherein the barrier layer also directly contacts a sidewall of the capacitor dielectric layer, and wherein the UBM layer covers the barrier layer; and

an isolation coating covering the MIM capacitor, the second interconnect structure, and the first UBM segment, wherein the isolation coating comprises an opening exposing the second UBM segment, and wherein the second UBM segment is spaced from sidewalls of the opening.

18. The package according to claim 17 ,

wherein the barrier layer comprises a plurality of discreet segments, and wherein one of the discreet segments has the same width as the first UBM segment.

19. The package according to claim 17 , wherein the barrier layer contacts sidewalls respectively of the capacitor dielectric layer and the second polymer layer, and wherein the barrier layer contacts a sidewall of the upper metal layer and contacts top surfaces respectively of the second polymer layer and the second interconnect structure.

20. The package according to claim 17 , further comprising:

a metal bump over and electrically coupled to the second interconnect structure of the plurality of interconnect structures through the second UBM segment, wherein the metal bump is in the opening and spaced from the sidewalls of the opening.