Method and apparatus for performing lossy integer multiplier synthesis
View Patent ↗A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture.
1. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving a Register Transfer Language (RTL) representation for a logic circuit for performing a multiplication as a sum of addends operation with a desired rounding precision, the method comprising:
determining an error requirement to be met for the desired rounding precision;
determining a number of columns k to be discarded from the sum of addends and a constant to include in the sum of addends for each of a CCT and VCT implementation of the sum of addends which meets the error requirement, and further determining a number of columns to discard for an LMS implementation of the sum of addends which meets the error requirement;
discarding columns according to the determined respective number of columns for each of the CCT, VCT and LMS implementations;
including the constant in the sum of addends for each of the CCT and VCT implementations;
deriving an RTL representation of the sum of addends operation for each of the CCT, VCT and LMS implementations, after performing the discarding and the including of the constant;
synthesizing a respective netlist for each of the respective RTL representations; and
selecting one of the synthesized netlists for production of a logic circuit.
2. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , wherein k and C are selected by maximizing the size of k and minimizing the number of binary ones in the binary expansion of C.
3. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 2 , wherein k CCT is a minimum hamming weight for all possible values of C that satisfy the condition that C be less than 2 (n−kCCT) and greater than (k CCT −2).
4. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , wherein the number of columns k for the CCT (k CCT ) implementation is a maximum of all values of k that satisfy the condition that 2 n is greater than (k−1)2 k .
5. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , wherein the number of columns k for the VCT implementation is a maximum of all values of k that satisfy the condition that 2 n is greater than (k−1)2 k .
6. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , wherein the number of columns k for the VCT implementation and the constant for the VCT implementation are selected as k VCT =max(k:∃Cs.t.3*2 n−k+1 −k−2>6C>k−7) and C VCT =min hamm(C:3*2 n−k VCT +1 −k VCT −2>6C>k VCT −7).
7. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , further comprising manufacturing an integrated circuit with the selected netlist.
8. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , further comprising maximizing k for both CCT and VCT implementations.
9. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , further comprising providing an additional error constraint on the selection of k and C parameters for one or more of the CCT, VCT and LMS implementations.
10. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , further comprising producing an error report including a worse case error for the resulting lossy multiplier netlist.
11. A non-transitory machine readable medium storing instructions for causing a machine to perform a method for deriving RTL for a logic circuit according to claim 1 , wherein for n=8, k for the CCT implementation is 5, C for the CCT implementation is 4, k for the VCT implementation is 6, C for the VCT implementation is 0, and k for the LMS implementation is 6.
12. A non-transitory machine readable medium storing machine executable instructions for a method, comprising:
determining an error requirement to be met for the desired rounding precision;
determining a number of columns k to be discarded from the sum of addends and a constant to include in the sum of addends for each of a CCT and VCT implementation of the sum of addends which meets the error requirement, and further determining a number of columns to discard for an LMS implementation of the sum of addends which meets the error requirement;
for each of the CCT, VCT and LMS implementations, discarding columns according to the determined number of columns;
for each of the CCT and VCT implementations, including the constant in the sum of addends;
deriving an RTL representation of the sum of addends operation for each of the CCT, VCT and LMS implementations, after performing the discarding and including of the constant;
synthesizing a respective netlist for each of the respective RTL representations; and
selecting one of the synthesized netlists.
13. The machine readable medium of claim 12 , wherein the method further comprises selecting k and C for the VCT implementation by maximizing the size of k and minimizing the number of binary ones in the binary expansion of C.
14. The machine readable medium of claim 12 , wherein the method further comprises selecting k and C for the CCT implementation by maximizing the size of k and minimizing the number of binary ones in the binary expansion of C.
15. The machine readable medium of claim 12 , wherein the number of columns k for the CCT (k CCT ) implementation is a maximum of all values of k that satisfy the condition tha*2t 2 n is greater than (k−1)2 k .
16. The machine readable medium of claim 15 , wherein according to claim 2 , wherein k CCT is a minimum hamming distance for all possible values of C that satisfy the condition that C be less than 2 (n−kCCT) and greater than (k CCT −2).
17. The machine readable medium of claim 12 , wherein the number of columns k for the VCT implementation (k vct ) is a maximum of all values of k that satisfy the condition that 2 n is greater than (k−1)2 k .
18. The machine readable medium of claim 12 , wherein k vct and the constant for the VCT (C VCT ) implementation are selected as k VCT =max(k:∃Cs.t.3*2 n−k+1 −k−2>6C>k−7) and C VCT =min hamm(C:3*2 n−k VCT +1 −k VCT −2>6C>k VCT −7).
19. The machine readable medium of claim 12 , further comprising manufacturing an integrated circuit with the selected netlist.
20. The machine readable medium of claim 12 , further comprising maximizing k for both CCT and VCT implementations.