Patent Assignment
Reel/Frame 068221/0001
Security Interest
Recorded: 2024-07-31
Pages: 75
Assignor
IMAGINATION TECHNOLOGIES LIMITED
Executed: 2024-07-30
Assignee
FORTRESS INVESTMENT GROUP (UK) LTD
C/O FORTRESS INVESTMENT GROUP, 1345 AVENUE OF THE AMERICAS, 46TH FLOOR, NEW YORK, NEW YORK, 10105
Covered Properties
(1356)
Method and Apparatus for Compressing Data and Decompressing Compressed Data
3D Vector Method of Inter-Field Motion Detection
Data Interface Register Structure with Registers for Data, Validity, Group Membership Indicator, and Ready to Accept Next Member Signal
System of Hardware Objects
Development System for an Integrated Circuit Having Standardized Hardware Objects
Method and Apparatus for Management of Control Flow in a Simd Device
Motion Compensation Deinterlacer Protection
Apparatus for Evaluating a Mathematical Function
Method and Apparatus for Removing Visible Artefacts in Video Images
Conversion of Video Data from Interlaced to Non-Interlaced Format
Conversion of Video Data from Interlaced to Non-Interlaced Format
Method and Apparatus for Controlling Overshoot in a Video Enhancement System
Development System for an Integrated Circuit Having Standardized Hardware Objects
System of Virtual Data Channels in an Integrated Circuit
Texturing 3-Dimensional Computer Graphic Images
Clock Generation for Multiple Clock Domains
Full Screen Anti-Aliasing with Dynamic Filters
Scalable Multi-Threaded Media Processing Architecture
Motion Estimation
Method and Apparatus for Scaling Down a Bayer Domain Image
Multi-Frequency Debug Network for a Multiprocessor Array
Automatic Color Calibration of an Image Sensor
Method and Apparatus for Rendering Computer Graphic Images of Translucent and Opaque Objects
Method and Apparatus for Determining Motion Between Video Images
Method and System to Reduce Flicker Artifacts in Captured Images
One-Dimensional Lens Shading Correction
Image Stabilization Method
Parameter Compaction in Tile Based Rendering Device
Synchronisation of Execution Threads on a Multi-Threaded Processor
Digital Electronic Binary Rotator and Reverser
Three Dimensional Graphics System with Early Occlusion Culling Using Z-Ranges
Memory Management for Systems for Generating 3-Dimensional Computer Images
System for Reconfiguring a Processor Array
Processing Long-Latency Instructions in a Pipelined Processor
Data Processing Modules Requiring Different Average Clock Frequencies Having a Common Clock and a Clock Gating Circuit for Deleting Clock Pulses Applied to the Modules at Times Consistent with Data Sourcing and Sinking Capabilities
Method and System for Data Compression
Compound Instructions in a Multi-Threaded Processor
Methods and Systems for Generating 3-Dimensional Computer Images
Method and Apparatus for Increasing Efficiency of Transmission and/or Storage of Rays for Parallelized Ray Intersection Testing
Method and Apparatus for Compressing and Decompressing Data
Tracing of Shader-Generated Ray Groups Using Coupled Intersection Testing
Multi-Core Geometry Processing in a Tile Based Rendering System
Apparatus and Method for Ray Tracing with Block Floating Point Data
Untransformed Display Lists in a Tile Based Rendering System
Architectures for Parallelized Intersection Testing and Shading for Ray-Tracing Rendering
Method of Decoding Data and Apparatus Therefor
Method, Apparatus, and Computer Readable Medium for Accelerating Intersection Testing in Ray-Tracing Rendering
Systems and Methods for Concurrent Ray Tracing
Ray Tracing System Architectures and Methods
Systems and Methods for a Ray Tracing Shader Api
Systems and Methods of Multidimensional Query Resolution and Computation Organization
Synthetic Acceleration Shapes for Use in Ray Tracing
Ray Tracing Using Ray-Specific Clipping
Object tracking using momentum and acceleration vectors in a motion estimation system
Method and Apparatus for Rendering a Computer-Generated Image
Systems and Methods for Photon Map Querying
Systems and Methods of Defining Rays for Ray Tracing Rendering
Two-Dimensional Lens Shading Correction
Lens Shading Correction for Autofocus and Zoom Lenses
Dynamic Ray Population Control
Architectures for Parallelized Intersection Testing and Shading for Ray-Tracing Rendering
Systems and Methods for Self-Intersection Avoidance in Ray Tracing
Skin Tone Detection in a Digital Camera
Method, Apparatus, and Computer Readable Medium for Light Energy Accounting in Ray Tracing
Object tracking using graphics engine derived vectors in a motion estimation system
Requests and Data Handling in a Bus Architecture
Processing of 3D computer graphics data on multiple shading engines
Memory Management System and Method
Method and Apparatus for Sharpening Digital Images
Video interpolation
Systems and Methods for Primitive Intersection in Ray Tracing
Tessellation of patches of surfaces in a tile based rendering system
Multilevel Display Control List in Tile Based 3D Computer Graphics System
Display List Control Stream Grouping in Tile Based 3D Computer Graphics System
Ray Tracing System Architectures and Methods
Method of Making Apparatus for Computing Multiple Sum of Products
Random accessible lossless parameter data compression for tile based 3D computer graphics systems
De-interlacing of video data
Variable-Sized Concurrent Grouping for Multiprocessing
Memory Allocation in Distributed Memories for Multiprocessing
Multi-Phased and Multi-Threaded Program Execution Based on Simd Ratio
Direct Ray Tracing of 3D Scenes
Method and Apparatus for Tile Based Depth Buffer Compression
Compression of a Tessellated Primitive Index List in a Tile Rendering System
Synchronisation of Execution Threads on a Multi-Threaded Processor
Processing Long-Latency Instructions in a Pipelined Processor
Architectures for Concurrent Graphics Processing Operations
Method and Apparatus for Determining Motion Between Video Images
Scheduling Heterogenous Computation on Multithreaded Processors
Method and Apparatus for Compressing and Decompressing Data
Ray Tracing System Architectures and Methods
Multi-Core Geometry Processing in a Tile Based Rendering System
Requests and Data Handling in a Bus Architecture
Method and Apparatus For Performing Lossy Integer Multiplier Synthesis
Systems and Methods for Rendering with Ray Tracing
Multistage Collector for Outputs in Multiprocessor Systems
External Vectors in a Motion Estimation System
Method and Apparatus for Use in the Design and Manufacture of Integrated Circuits
Method and Apparatus for Controlling Overshoot in a Video Enhancement System
Method and Apparatus for Rendering a Computer Generated Image
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
Profiling Ray Tracing Renderers
Detecting Image Impairments in an Interpolated Image
Rendering a Scene Using a Reduced Memory Representation of a Polynomial Function to Determine an Output Value Approximating a Mathematical Function
Method and Apparatus for Time Synchronisation in Wireless Networks
Systems and Methods for Concurrent Ray Tracing
Method and Apparatus for Performing Formal Verification of Polynomial Datapath
Method and System for Multisample Antialiasing
Untransformed Display Lists in a Tile Based Rendering System
Decoding Successive Motion Compensated Video Sequence Images in Parallel Using Data Corresponding to Maximum Extent of a Motion Vector
Graphics Processor with Non-Blocking Concurrent Architecture
Method and Apparatus for Synthesising a Sum of Addends Operation and an Integrated Circuit
Unified Rasterization and Ray Tracing Rendering Environments
Systems and Methods of Partial Frame Buffer Updating
Pixel Buffering
Compacting Results Vectors Between Stages of Graphics Processing
Multi-Core Geometry Processing in a Tile Based Rendering System
Tile Based Computer Graphics
Systems and Methods for Program Interfaces in Multipass Rendering
Method and System for Wirelessly Transmitting Data
Method, System and Device for Selecting a Device to Satisfy a User Request
Dynamic Graphics Rendering Scheduling
System and Methods for Generating Variable Frequency Clock Signals from Common Clock Signal and Usage Threof
Memory Efficient Progressive Refinement in Ray Tracing
Method and Apparatus for Compressing and Decompressing Data
Compression of a Tessellated Primitive Index List in a Tile Rendering System
Tessellating Patches of Surface Data in Tile Based Computer Graphics Rendering
Method and Apparatus for Time Synchronisation in Wireless Networks
Pixel Clustering
Requests and Data Handling in a Bus Architecture
Ray Tracing System Architectures and Methods
Method and Apparatus for Determining Motion Between Video Images
Conversion of a Normalized N-Bit Value into a Normalized M-Bit Value
System and Method of Arbitrating Access to Interconnect
Hidden Culling in Tile-Based Computer Generated Images
Constant Fraction Integer Multiplication
Tile-Based Graphics
3-D Graphics Rendering with Implicit Geometry
Synchronisation of Execution Threads on a Multi-Threaded Processor
Graphics Processor with Non-Blocking Concurrent Architecture
Building Acceleration Structures with Synthetic Acceleration Shapes for Use in Ray Tracing
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
Rendering with Point Sampling and Pre-Computed Light Transport Information
Object Tracking Using Graphics Engine Derived Vectors in a Motion Estimation System
Relightable Texture for Use in Rendering an Image
Vertex Parameter Data Compression
Untransformed Display Lists in a Tile Based Rendering System
Method and Apparatus for Compressing and Decompressing Data
Encoding an Image
Encoding an Image
Normal Offset Smoothing
Generating an Output Frame for Inclusion in a Video Sequence
Multi-Line Image Processing with Parallel Processing Units
Atomic Memory Update Unit & Methods
Random Accessible Lossless Parameter Data Compression for Tile Based 3D Computer Graphics Systems
Skin Colour Probability Map
Face Detection in an Image Data Stream Using Skin Colour Patch Constructs
Correcting Chrominance Values Based onTone-Mapped Luminance Values
Tone Mapping
Processor with Ray Test Instructions Performed by Special Purpose Units
Defective Pixel Fixing
Task Execution in a SIMD Processing Unit
Task Execution in a SIMD Processing Unit with Parallel Groups of Processing Lanes
Primitive Processing in a Graphics Processing System
Primitive Processing in a Graphics Processing System With Tag Buffer Storage of Primitive Identifiers
Partially and Fully Parallel Normaliser
Trailing or Leading Zero Counter Having Parallel and Combinational Logic
Proximity Detection
Opacity Testing For Processing Primitives In A 3D Graphics Processing System
Processing of Primitive Blocks in Parallel Tiling Engine Pipes
Dynamic Graphics Rendering Scheduling
Image Sensor Gamut Mapping
Rendering of Soft Shadows
Error Tracking and Mitigation for Motion Compensation-Based Video Compression
Object Illumination in Hybrid Rasterization and Ray Traced 3-D Rendering
Exchanging Configuration Information Wirelessly
High Definition Timing Synchronisation Function
Clock Verification
Virtual Camera for 3-D Modeling Applications
Compacting Results Vectors Between Stages of Graphics Processing
On Demand Geometry and Acceleration Structure Creation
Noise Enhanced Histograms
Approximating Functions
Cadence Analysis for a Video Signal Having an Interlaced Format
Time Stamp Replication Within a Wireless Network
Graphics Processor with Non-Blocking Concurrent Architecture
Object tracking using momentum and acceleration vectors in a motion estimation system
Allocation of Primitives to Primitive Blocks
Relightable texture for use in rendering an image
Gamut Mapping with Blended Scaling and Clamping
Setting A Display List Pointer for Primitives in a Tile-Based Graphics Processing System
Assigning Primitives to Tiles in a Graphics Processing System
Error Detection in a Motion Estimation System
Replicating Logic Blocks to Enable Increased Throughput with Sequential Enabling of Input Register Blocks
Profiling Ray Tracing Renderers
Check Procedure for Floating Point Operations
Biasing Selection of Motion Estimation Vectors
Local irradiance estimation for use in rendering an image
Implementing a Square Root Operation in a Computer System
Performing a Comparison Computation in a Computer System
Determining Diffuse Image Component Values for Use in Rendering an Image
Surface normal estimation for use in rendering an image
Ray Tracing System Architectures and Methods
Hardware Data Structure for Tracking Ordered Transactions
Hardware Data Structure for Tracking Partially Ordered and Reordered Transactions
Efficient Interpolation
Combining Instructions from Different Branches for Execution in a Single N-Way Vliw Processing Element of a Multithreaded Processor
Evaluation of Polynomials with Floating-Point Components
Method and System for Staggered Parallelized Video Decoding
Data Compression Using Entropy Encoding
Data Compression Using Spatial Decorrelation
Cache Hashing
Presenting Pipelines of Multicore Processors as Separate Processor Cores to a Programming Framework
Rounding Floating Point Numbers
Variable Length Execution Pipeline
Using Tiling Depth Information in Hidden Surface Removal in a Graphics Processing System
Implementing Fixed-Point Polynomials in Hardware Logic
Small Multiplier After Initial Approximation for Operations with Increasing Precision
Method, System and Device for Selecting a Device to Satisfy a User Request
Method and System for Wirelessly Transmitting Data
Random Accessible Lossless Parameter Data Compression for Tile Based 3D Computer Graphics Systems
Method and System for Multisample Antialiasing
Proximity Detection
Performing Object Detection in an Image
Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio
Unified Multiply Unit
Building Acceleration Structures with Synthetic Acceleration Shapes for Use in Ray Tracing
Arbiter Verification
Processing Primitives Which Have Unresolved Fragments in a Graphics Processing System
Rendering Views of a Scene in a Graphics Processing Unit
Low Power Detection of a Voice Control Activation Phrase
Systems and Methods for Distributed Scalable Ray Processing
Systems and Methods for Soft Shadowing in 3-D Rendering
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Image Noise Reduction Using Lucas Kanade Inverse Algorithm
Image Noise Reduction
Unified Rasterization and Ray Tracing Rendering Environments
Untransformed Display Lists in a Tile Based Rendering System
Image Filtering Based on Image Gradients
Modulo Calculation Using Polynomials
Image Synthesis
Deadlock Detection in Hardware Design Using Assertion Based Verification
Tiling a Primitive in a Graphics Processing System by Testing Subsets of Tiles in a Rendering Space
Tiling a Primitive in a Graphics Processing System
Control Path Verification of Hardware Design for Pipelined Process
Performing Constant Modulo Arithmetic
Graphics Processor with Non-Blocking Concurrent Architecture
Trailing or Leading Zero Counter Having Parallel and Combinational Logic
Error Tracking and Mitigation for Motion Compensation-Based Video Compression
Efficient Modulo Calculation
Method and Apparatus for Time Synchronisation in Wireless Networks
Tessellation Method
Tessellation Method Using Recursive Sub-Division of Triangles
Tessellation Method Using Displacement Factors
Motion Estimation Using Collocated Blocks
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
Clock Frequency Adjustment for Semi-Conductor Devices
Atomic Memory Update Unit & Methods
Rounding Floating Point Numbers
Denoising Filter
Hardware Data Structure for Tracking Ordered Transactions
Processing of Primitive Blocks in Parallel Tiling Engine Pipes
Synchronising Devices Using Clock Signal Delay Comparison
Synchronising Devices Using Clock Signal Time Difference Estimation
Graphics Processing Method and System for Processing Sub-Primitives Using Cached Graphics Data Hierarchy
Graphics Processing Method and System for Processing Sub-Primitives Using Sub-Primitive Indications in a Control Stream
Synchronising Devices Using Clock Signal Delay Estimation
Method and Apparatus for Compressing and Decompressing Data
Task Execution in a Simd Processing Unit with Parallel Groups of Processing Lanes
Trailing or Leading Digit Anticipator
Data Compression Using Spatial Decorrelation
Tessellating Patches of Surface Data in Tile Based Computer Graphics Rendering
Variable Length Execution Pipeline
Asynchronous and Concurrent Ray Tracing and Rasterization Rendering Processes
System and Method for Rounding Reciprocal Square Root Results of Input Floating Point Numbers
Systems and Methods for Processing Images of Objects Using Global Lighting Estimates
Systems and Methods for Processing Images of Objects Using Coarse Surface Normal Estimates
Systems and Methods for Processing Images of Objects Using Coarse Intrinsic Colour Estimates
Systems and Methods for Processing Images of Objects Using Interpolation Between Keyframes
Systems and Methods for Processing Images of Objects Using Lighting Keyframes
Clock Verification
Multi-Line Image Processing with Parallel Processing Units
Hardware Monitor to Verify Memory Units
Tile-Based Graphics
Trailing or Leading Zero Counter Having Parallel and Combinational Logic
Modulo Hardware Generator
Relightable texture for use in rendering an image
Gpu Virtualisation
Foveated Rendering
Multistage Collector for Outputs in Multiprocessor Systems
Tile Based Computer Graphics
Arbiter Verification
Artefact Detection and Correction
Capturing an Image
Allocation of Tiles to Processing Engines in a Graphics Processing System
Lossy Data Compression
Face Detection in an Image Data Stream Using Skin Colour Patch Constructs
Controlling the Focus of a Camera Using Focus Statistics
Rendering in Computer Graphics Systems
Dynamic Power Measurement Using Formal
Identifying Bugs in a Counter Using Formal
Frustum Rendering in Computer Graphics
Sparse Rendering in Computer Graphics
Compacting Results Vectors Between Stages of Graphics Processing
Task Assembly for SIMD Processing
Constant Fraction Integer Multiplication
Methods and Graphics Processing Units for Determining Differential Data for Rays of a Ray Bundle
Importance Sampling for Determining a Light Map
Check Procedure for Floating Point Operations
Non-Linear Cache Logic
Hierarchy Merging
Query Resolver for Global Illumination of 3-D Rendering
Unified Multiply Unit
Generating Sparse Sample Histograms in Image Processing
Learned Feature Motion Detection
Noise Enhanced Histograms
Handling Memory Requests
Systems and Methods of Partial Frame Buffer Updating
Partially and Fully Parallel Normaliser
Dedicated Ray Memory for Ray Tracing in Graphics Systems
Sorting Numbers in Hardware
Evaluating Polynomials in Hardware Logic
Communications Interface Circuit Architecture
Circuit Architecture Mapping Signals to Functions for State Machine Execution
Generation of a Control Stream for a Tile
Verification of Hardware Designs to Implement Floating Point Power Functions
Primitive Processing in a Graphics Processing System With Tag Buffer Storage of Primitive Identifiers
Compressing and Decompressing Image Data Using Compacted Region Transforms
Hardware Implementation of a Convolutional Neural Network
Convolutional Neural Network Hardware Configuration
Primitive Processing in a Graphics Processing System
Hardware Data Structure for Tracking Partially Ordered and Reordered Transactions
Assessing Performance of a Hardware Design Using Formal Evaluation Logic
Deadlock Detection in Hardware Design Using Assertion Based Verification
Executing Memory Requests Out of Order
Method and Apparatus for Compressing and Decompressing Data
Approximating Functions
Livelock Detection in a Hardware Design Using Formal Evaluation Logic
Augmented Reality Occlusion
Livelock Recovery Circuit Configured to Detect Illegal Repetition of an Instruction and Transition to a Known State
Low Power Detection of a Voice Control Activation Phrase
Low-Area Fixed-Point Polynomials
Error Bounded Multiplication by Invariant Rationals
Method and Apparatus for Time Synchronisation in Wireless Networks
Master Synchronisation
Clock Synchronisation
Reference Synchronisation
MIP Map Compression
Tessellation of Patches of Surfaces in a Tile Based Rendering System
Processing Primitives Which Have Unresolved Fragments in a Graphics Processing System
Systems and Methods for Distributed Scalable Ray Processing
Image Filtering Based on Image Gradients
Trailing or Leading Zero Counter Having Parallel and Combinational Logic
Data Compression Using Spatial Decorrelation
Task Scheduling in a GPU
Buffer Addressing for a Convolutional Neural Network
Hidden Culling in Tile-Based Computer Generated Images
Performing Object Detection in an Image
Detecting Out-of-Bounds Violations in a Hardware Design Using Formal Verification
Out-Of-Bounds Recovery Circuit
Verifying Firmware Binary Images Using a Hardware Design and Formal Assertions
Division Synthesis
Performing a Comparison Computation in a Computer System
Encoding and Decoding Variable Length Instructions
Image Noise Reduction
Performance Profiling in Computer Graphics
Rendering a Computer Generated Image Using a Stencil Buffer
Rendering a Computer Generated Image Using a Stencil Buffer with Primitive Concatenation
Tile-Based Graphics
Median Value Determination in a Data Processing System
Efficient Catmull-Rom Interpolation
Patent:
10,102,181 →
Application:
15/909,671 →
Efficient Interpolation Using Not Linear Interpolation
Tessellating Patches of Surface Data in Tile Based Computer Graphics Rendering
Graphics Processing Units and Methods Using Cost Indications for Sets of Tiles of a Rendering Space
Graphics Processing Units and Methods for Subdividing a Set of One or More Tiles of a Rendering Space for Rendering
Computing Systems and Methods for Processing Graphics Data Using Cost Indications for Sets of Tiles of a Rendering Space
Graphics Processing Units and Methods for Controlling Rendering Complexity Using Cost Indications for Sets of Tiles of a Rendering Space
Selection of Data for Processor Pipelines Using Multiple Supply Lines Wherein in One of Two Modes the Same Data is Supplied to Both Inputs of a Processing Element
Formal Verification of Integrated Circuit Hardware Designs to Implement Integer Division
Untransformed Display Lists in a Tile Based Rendering System
Tessellation Method
Cadence Analysis for a Video Signal Having an Interlaced Format
Method and Apparatus for Use in the Design and Manufacture of Integrated Circuits
Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
On Demand Geometry and Acceleration Structure Creation with Discrete Production Scheduling
On Demand Geometry and Acceleration Structure Creation with Tile Object Lists
Proximity Detection
Time Stamp Replication Within a Wireless Network Using Error Calculation
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Graphics Processing Method and System for Processing Sub-Primitives
Floating Point to Fixed Point Conversion
Floating Point to Fixed Point Conversion Using Exponent Offset
Camera Calibration
Parallel Computing Architecture for Use with a Non-Greedy Scheduling Algorithm
Trailing or Leading Zero Counter Having Parallel and Combinational Logic
Systems and Methods for Soft Shadowing in 3-D Rendering Using Identification of Nearest-Hit Primitive
Systems and Methods for Soft Shadowing in 3-D Rendering Using Directionalized Distance Function
Decoder Unit for Texture Decompression
Multi-Output Decoder for Texture Decompression
Allocation of Tiles to Processing Engines in a Graphics Processing System
Asynchronous and Concurrent Ray Tracing and Rasterization Rendering Processes
Object Illumination in Hybrid Rasterization and Ray Traced 3-D Rendering
Assigning Primitives to Tiles in a Graphics Processing System
Compressed Ray Direction Data in a Ray Tracing System
Methods and Graphics Processing Units for Determining Differential Data for Rays of a Ray Bundle
Synchronizing Scheduling Tasks with Atomic Alu
Scheduling Tasks Using Work Fullness Counter
Methods and Systems for Inter-Pipeline Data Hazard Avoidance
Controlling Scheduling of a Gpu
Scheduling Tasks Using Swap Flags
Scheduling Tasks Using Targeted Pipelines
Controlling Operation of a Gpu
On Demand Geometry and Acceleration Structure Creation
Tessellation Method Using Recursive Sub-Division of Triangles
Controlling the Focus of a Camera Using Focus Statistics
Multi-viewpoint Transformation Module for use in 3D Rendering System
Hybrid Hierarchy of Bounding and Grid Structures for Ray Tracing
Hybrid Hierarchy of Bounding and Grid Structures for Ray Tracing
Upscaling Lower Resolution Image Data for Processing
Low Power Detection of a Voice Control Activation Phrase
Efficient Modulo Calculation
Trailing or Leading Digit Anticipator
Method and System for Wirelessly Transmitting Data
Generation of a Control Stream for a Tile
Rendering a 3-D Scene Using Normal Offset Smoothing
Low Latency Distortion Unit for Head Mounted Displays
Single Pass Rendering for Head Mounted Displays
Luminance-Normalised Colour Spaces
Reduced Acceleration Structures for Ray Tracing Systems
Allocation of Memory Resources to Simd Workgroups
Tessellation Method
Sorting Memory Address Requests for Parallel Memory Access
Constructing an Image Using More Pixel Data than Pixels in an Image Sensor
Compressing Blocks of Data Values by Performing Spatial Decorrelation on Reorganized Blocks
Geometry to Tiling Arbiter for Tile-Based Rendering System
Compressing M-Bit Data Using Spatial Decorrelation and Entropy Encoding on N-Bit Data
Ray Tracing in Computer Graphics Using Intersection Testing at Selective Resolution
Rendering a Computer Generated Image Using a Stencil Buffer with Vertex Index Offset
Interpolating a Sample Value in a Data Array by Linear Interpolation of Surrounding Interpolated Values
Systems and Methods for Processing a Stream of Data Values Using Data Value Subset Groups
Processing Received Pixel Values in an Image Processing System Using Pixel Value Subset Groups
Processing a Stream of Pixel Values in an Image Processing System Using Pixel Value Subset Groups
Processing Received Pixel Values in an Image Processing System Using Pixel Subset Average Values of Grouped Subsets
Primitive Processing in a Graphics Processing System With Tag Buffer Storage of Primitive Identifiers
Allocation of Tiles to Processing Engines in a Graphics Processing System
Data Compression Using Entropy Encoding
Hardware Implementation of Convolutional Layer of Deep Neural Network
Unified Rasterization and Ray Tracing Rendering Environments
Verification of Hardware Designs to Implement Floating Point Power Functions
Neural Network Architecture Using Convolution Engine Filter Weight Buffers
Method and Apparatus for Implementing a Deep Neural Network Performing an Activation Function
Neural Network Architecture Using Convolution Engines
Neural Network Architecture Using Single Plane Filters
Neural Network Architecture Using Control Logic Determining Convolution Operation Sequence
Synchronisation of Execution Threads on a Multi-Threaded Processor
Rendering in Computer Graphics Systems
Rendering of Soft Shadows
Tessellation Method Using Displacement Factors
Handling Memory Requests
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
Multistage Collector for Outputs in Multiprocessor Systems
Partially and Fully Parallel Normaliser
Denoising Filter
Modulo Hardware Generator
Method and Apparatus for Use in the Design and Manufacture of Integrated Circuits
Virtual Camera for 3-D Modeling Applications
Task Assembly for SIMD Processing
Assembling Primitive Data into Multi-view Primitive Blocks in a Graphics Processing System
Approximating Functions
Method and apparatus for rendering a computer generated image
Tiling a Primitive in a Graphics Processing System by Edge-Specific Testing of a Subset of Tiles in a Rendering Space
Topology Preservation in a Graphics Pipeline
Error Allocation Format Selection for Hardware Implementation of Deep Neural Network
Hardware Unit for Performing Matrix Multiplication with Clock Gating
Histogram-Based Per-Layer Data Format Selection for Hardware Implementation of Deep Neural Network
Foveated Rendering
Compressed Ray Direction Data in a Ray Tracing System
Compressed Ray Direction Data in a Ray Tracing System
End-to-End Data Format Selection for Hardware Implementation of Deep Neural Networks
Task Execution in a Simd Processing Unit with Parallel Groups of Processing Lanes
Generating Sparse Sample Histograms in Image Processing
Error Bounded Multiplication by Invariant Rationals
Biasing Selection of Motion Estimation Vectors
Control Path Verification of Hardware Design for Pipelined Process
Importance Sampling for Determining a Light Map
Dedicated Ray Memory for Ray Tracing in Graphics Systems
Task Scheduling in a GPU
Memory Interface Having Multiple Snoop Processors
Memory Interface Between Physical and Virtual Address Spaces
Data Coherency Manager with Mapping Between Physical and Virtual Address Spaces
High Definition Timing Synchronisation Function
Livelock Detection in a Hardware Design Using Formal Evaluation Logic
Assessing Performance of a Hardware Design Using Formal Evaluation Logic
Compressed Mip Map Decoding Method and Decoder with Bilinear Filtering
Compressed Mip Map Decoding Method and Decoder
Trailing or Leading Digit Anticipator
Synchronisation of Hardware Clock Using Software Clock Synchronisation Error
Clock Synchronisation Between Devices Using Third Device
Clock Verification
Gpu Virtualisation
Arbitrating Requests for Access to a Computer Resource by Ordered Requestors
Common Priority Information for Multiple Resource Arbitration
Modifying Processing of Commands in a Command Queue Based on Subsequently Received Data
Verifying a Hardware Design for a Component that Implements a Permutation Respecting Function
Tessellation Method
Edge Test and Depth Calculation in Graphics Processing Hardware
Texture Filtering with Dynamic Scheduling in Computer Graphics
Verification of Hardware Design for Data Transformation Pipeline with Equivalent Data Transformation Element Output Constraint
Ordering of Patch Selection in Tessellation Operations
Tessellation Hardware Subdivision of Patches Into Sub-Patches
Post-Tessellation Blending in a Gpu Pipeline
Matching Local Image Feature Descriptors in Image Analysis
Verification of Hardware Design for Data Transformation Pipeline
Evaluating a Mathematical Function in a Computational Environment
Sampling for Feature Detection in Image Analysis
Generating Feature Descriptors for Image Analysis
Random Accessible Lossless Parameter Data Compression for Tile Based 3D Computer Graphics Systems
Hidden Culling in Tile-Based Computer Generated Images
Compressing and Decompressing Image Data Using Compacted Region Transforms
Performing Constant Modulo Arithmetic
Controlling the Focus of a Camera Using Focus Statistics
Learned Feature Motion Detection
Computing Systems and Methods for Processing Graphics Data Using Cost Indications for Sets of Tiles of a Rendering Space
Approximating Functions
Hybrid Hierarchy of Bounding and Grid Structures for Ray Tracing
Implementing Traditional Computer Vision Algorithms as Neural Networks
Rendering in Computer Graphics Systems
Vertex Processing Pipeline for Building Reduced Acceleration Structures for Ray Tracing Systems
Determining Lighting Information for Rendering a Scene in Computer Graphics Using Illumination Point Sampling
Bilateral Filter with Data Model
Producing Rendering Outputs from a 3-D Scene Using Volume Element Light Transport Data
Graphics Processing Method and System for Processing Sub-Primitives
Guaranteed Data Compression
Guaranteed Data Compression
Guaranteed Data Compression
Conservative Rasterization
Conservative Rasterization Using Gradients
Guaranteed Data Compression
Guaranteed Data Compression
Guaranteed Data Compression
Tile Assignment to Processing Cores Within a Graphics Processing Unit
Virtual Memory Management
Image Component Detection
Clock Frequency Adjustment For Semi-Conductor Devices
Tile Based Computer Graphics
Rendering a 3-D Scene Using Secondary Ray Tracing
Scalable Parallel Tessellation
Median Value Determination in a Data Processing System
Frustum Rendering in Computer Graphics
Method and Apparatus for Time Synchronisation in Wireless Networks
Tiling a Primitive in a Graphics Processing System by Edge-Specific Testing of a Subset of Tiles in a Rendering Space
Float Division by Constant Integer
Task Scheduling in a GPU Using Wakeup Event State Data
Formal Verification of Integrated Circuit Hardware Designs to Implement Integer Division
Using Tiling Depth Information in Hidden Surface Removal in a Graphics Processing System
Method and Apparatus for Use in the Design and Manufacture of Integrated Circuits
Primitive Processing in a Graphics Processing System
Edge Test and Depth Calculation in Graphics Processing Hardware
Systems and Methods for Soft Shadowing in 3-D Rendering
Compiling and Combining Instructions from Different Branches for Execution in a Processing Element of a Multithreaded Processor
Systems and Methods for Soft Shadowing in 3-D Rendering Casting Multiple Rays from Ray Origins
Efficient Modulo Calculation
Selecting an Ith Largest or a Pth Smallest Number from a Set of N M-Bit Numbers
Processing Primitives Which Have Unresolved Fragments in a Graphics Processing System
Floating Point to Fixed Point Conversion
Livelock Recovery Circuit for Detecting Illegal Repetition of an Instruction and Transitioning to a Known State
Floating Point to Fixed Point Conversion Using Exponent Offset
Image Filtering Based on Image Gradients
Untransformed Display Lists in a Tile Based Rendering System
Graphics Processing Units and Methods for Controlling Rendering Complexity Using Cost Indications for Sets of Tiles of a Rendering Space
Data Compression and Storage
Workload Repetition Redundancy
Buffer Checker for Task Processing Fault Detection
Trailing or Leading Digit Anticipator
Formal Verification Tool to Verify Hardware Design of Memory Unit
Communications Interface Between Host System and State Machine
Generating an Augmented Reality Image Using a Blending Factor
Encoding and Decoding Variable Length Instructions
Performing Object Detection in an Image
Error Bounded Multiplication by Invariant Rationals
Texture Filtering with Dynamic Scheduling in Computer Graphics
Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio
Decoder Unit for Texture Decompression
ASTC Interpolation
Transformed Geometry Data Cache for Graphics Processing Systems
Primitive Block-Based Rasterization in Graphics Processing Systems
Tile-Based Scheduling
ASTC Interpolation
Primitive Block Generator for Graphics Processing Systems
Iterative Estimation Hardware
Double-Angle Gradients
Scheduling Tasks in a Processor
Methods and Systems for Selecting Quantisation Parameters for Deep Neural Networks Using Back-Propagation
Modulo Hardware Generator
Rendering of Soft Shadows
Sorting Memory Address Requests for Parallel Memory Access Using Input Address Match Masks
Method and System for Multisample Antialiasing
Graphics Processing Systems with Expansion Transformation Stage Masks
Memory for Storing Untransformed Primitive Blocks
Hidden Culling in Tile-Based Computer Generated Images
Encoding Images Using Mip Map Compression
Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Primitive Processing in a Graphics Processing System With Tag Buffer Storage of Primitive Identifiers
Task Execution in a Simd Processing Unit with Parallel Groups of Processing Lanes
Object Illumination in Hybrid Rasterization and Ray Traced 3-D Rendering
Image Noise Reduction
Allocation of Memory by Mapping Registers Referenced by Different Instances of a Task to Individual Logical Memories
Allocation of Memory
Tile Based Computer Graphics
Systems and Methods for Distributed Scalable Ray Processing
Performing Constant Modulo Arithmetic
Lossy Data Compression
Multi-viewpoint Transformation Module for use in 3D Rendering System
Floating Point to Fixed Point Conversion
Biasing Selection of Motion Estimation Vectors
Guaranteed Data Compression Using Intermediate Compressed Data
Partially and Fully Parallel Normaliser
Assigning Primitives to Tiles in a Graphics Processing System
Tessellation Method Using Vertex Tessellation Factors
Tessellation Method Using Recursive Sub-Division of Triangles
Verification of Hardware Design for Data Transformation Pipeline with Equivalent Data Transformation Element Output Constraint
Methods and Systems for Implementing a Convolution Transpose Layer of a Neural Network
Guaranteed Data Compression
Asynchronous and Concurrent Ray Tracing and Rasterization Rendering Processes
Time Stamp Replication Within a Wireless Network Based on Transmission Prediction
Interpolating a Sample Position Value by Interpolating Surrounding Interpolated Positions
Scheduling Tasks Using Work Fullness Counter
Modifying Processing of Commands in a Command Queue Based on Subsequently Received Data
Verification of Hardware Design for Integrated Circuit Implementing Polynomial Input Variable Function
Geometry to Tiling Arbiter for Tile-Based Rendering System
Gamut Mapping with Blended Scaling and Clamping
Tiling a Primitive in a Graphics Processing System by Edge-Specific Testing of a Subset of Tiles in a Rendering Space
Generation of a Control Stream for a Tile
Method and System for Wirelessly Transmitting Data
Detecting Out-of-Bounds Violations in a Hardware Design Using Formal Verification
Floating Point to Fixed Point Conversion Using Exponent Offset
Guaranteed Data Compression
Method and Apparatus for Rendering a Computer Generated Image
Noise Enhanced Histograms
Edge Test and Depth Calculation in Graphics Processing Hardware
Accessing Primitive Data Using Tessellated Primitive ID
Multi-Rendering in Graphics Processing Units Using Render Progression Checks
Controlling Rendering Operations by Shader Buffer Identification
Rendering Optimisation by Recompiling Shader Instructions
Multistage Collector for Outputs in Multiprocessor Systems
Primitive Fragment Processing in the Rasterization Phase of a Graphics Processing System
Coarse Depth Test in Graphics Processing Systems
Gpu Virtualisation
Synchronisation of Hardware Clock Using Software Clock Synchronisation Error
Out-Of-Bounds Recovery Circuit
Guaranteed Data Compression
Denoising Filter
Task Assembly for SIMD Processing
Tile Based Computer Graphics
Tessellation Method Using Displacement Factors
Allocation of Primitives to Primitive Blocks
Methods and Systems for Inter-Pipeline Data Hazard Avoidance
Virtual Camera for 3-D Modeling Applications
Guaranteed Data Compression
Apparatus and Method for Processing Floating-Point Numbers
Single Pass Rendering for Head Mounted Displays
Apparatus and Method for Processing Floating-Point Numbers
Rendering in Computer Graphics Systems
Assembling Primitive Data into Multi-View Primitive Blocks in a Graphics Processing System
Conservative Rasterization
Methods and Decompression Units for Decompressing a Compressed Block of Image Data
Graphics Processor with Non-Blocking Concurrent Architecture
Primitive Processing in a Graphics Processing System
Guaranteed Data Compression
Synchronizing Scheduling Tasks with Atomic Alu
Conservative Rasterization Using Gradients
Methods and Systems for Converting Weights of a Deep Neural Network from a First Number Format to a Second Number Format
Image Data Decompression
Image Data Compression
Random Accessible Image Data Compression
Performing Constant Modulo Arithmetic
Data Selection for a Processor Pipeline Using Multiple Supply Lines
Scheduling Tasks Using Swap Flags
Matching Local Image Feature Descriptors in Image Analysis
Rendering of Soft Shadows
Graphics Processing Units and Methods for Controlling Rendering Complexity Using Cost Indications for Sets of Tiles of a Rendering Space
Verification of Hardware Design for Data Transformation Component
Computing Systems and Methods for Processing Graphics Data Using Cost Indications for Sets of Tiles of a Rendering Space
Scheduling Tasks Using Targeted Pipelines
Hierarchical Tiling in a Graphics Processing System Using Chain Sorting of Primitives
Periodic Reset of Graphics Processor Unit in Safety-Critical Graphics Processing System
Livelock Detection in a Hardware Design Using Formal Evaluation Logic
Frustum Rendering in Computer Graphics
Circuit Architecture Mapping Signals to Functions for State Machine Execution
Ordering of Patch Selection in Tessellation Operations
Anisotropic Texture Filtering for Sampling Points in Screen Space
Error Allocation Format Selection for Hardware Implementation of Deep Neural Network
Unified Rasterization and Ray Tracing Rendering Environments
Handling Memory Requests
Median Value Determination in a Data Processing System
Floating Point to Fixed Point Conversion
Normal offset smoothing
Systems and Methods for Distributed Scalable Ray Processing
Arbitrating Requests for Access to a Computer Resource by Ordered Requestors
Post-Tessellation Blending in a Gpu Pipeline
Generating Sparse Sample Histograms in Image Processing
Memory Interface Between Physical and Virtual Address Spaces
Multi-Output Decoder for Texture Decompression
Verifying Firmware Binary Images Using a Hardware Design and Formal Assertions
On Demand Geometry and Acceleration Structure Creation with Tile Object Lists
Control Path Verification of Hardware Design for Pipelined Process
Clock Synchronisation Between Devices Using Message Timestamps
Hardware Implementation of Convolutional Layer of Deep Neural Network
Detecting Out-of-Bounds Violations in a Hardware Design Using Formal Verification
Error Bounded Multiplication by Invariant Rationals
Hybrid Hierarchy of Bounding and Grid Structures for Ray Tracing
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
3-D Graphics Rendering with Implicit Geometry
Assessing Performance of a Hardware Design Using Formal Evaluation Logic
Trailing or Leading Digit Anticipator
Floating Point to Fixed Point Conversion Using Exponent Offset
Multi-viewpoint Transformation Module for use in 3D Rendering System
Data Compression and Storage
Partially and Fully Parallel Normaliser
Rendering Views of a Scene in a Graphics Processing Unit
Methods and Systems for Storing Variable Length Data Blocks in Memory
Small Multiplier After Initial Approximation for Operations with Increasing Precision
Guaranteed Data Compression Using Intermediate Compressed Data
Rasterising Aliased Lines
Verifying a Hardware Design for a Multi-Stage Component
Addressing Read and Write Registers in an Event Slot of a Communications Interface with a Single Address by a Host System and Individually Addressable by a State Machine
Allocation of Memory Resources to Simd Workgroups
Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
Motion Estimation Using Collocated Blocks
Tessellation Hardware Subdivision of Patches Into Sub-Patches
Untransformed Display Lists in a Tile Based Rendering System
Methods and Control Stream Generators for Generating a Control Stream for a Tile Group in a Graphics Processing System
Data Structures, Methods and Tiling Engines for Storing Tiling Information in a Graphics Processing System
Data Structures, Methods and Tiling Engines for Hierarchically Storing Tiling Information in a Graphics Processing System
Data Structures, Methods and Primitive Block Generators for Storing Primitives in a Graphics Processing System
Implementing Fixed-Point Polynomials in Hardware Logic
Importance Sampling for Determining a Light Map
Graphics Processing Method and System for Rendering Items of Geometry Based on Their Size
Methods and Tiling Engines for Tiling Primitives in a Graphics Processing System
Critical Workload Check
Critical Workload Check
Look Ahead Normaliser
Graphics Processing Method and System for Rendering Items of Geometry Based on Their Size
Random Accessible Lossless Parameter Data Compression for Tile Based 3D Computer Graphics Systems
Systems and Methods for Soft Shadowing in 3-D Rendering Casting Multiple Rays from Ray Origins
Out-Of-Bounds Recovery Circuit
Decoder Unit for Texture Decompression
Data Coherency Manager with Mapping Between Physical and Virtual Address Spaces
Virtual Memory Management
Primitive Fragment Processing in the Rasterization Phase of a Graphics Processing System
Method and System for Verifying a Sorter
Learned Feature Motion Detection
Image Data Decompression
Stereoscopic Graphics Processing
Image Data Compression
Bilateral Filter with Data Model
Scalable Parallel Tessellation
Using Tiling Depth Information in Hidden Surface Removal in a Graphics Processing System
Image Component Detection
Guaranteed Data Compression
Verification of Hardware Design for Integrated Circuit Implementing Polynomial Input Variable Function
Verification of Hardware Design for Data Transformation Component
Efficient Encoding Methods Using Bit Inversion and Padding Bits
Priority Based Arbitration
Priority Based Arbitration
Low Latency Distortion Unit for Head Mounted Displays
ASTC Interpolation
Generating an Augmented Reality Image Using a Blending Factor
Compressing and Decompressing Image Data Using Compacted Region Transforms
Maintaining Synchronisation Between Memory Writing and Reading Blocks Using an Internal Buffer and a Control Channel
Asynchronous and Concurrent Ray Tracing and Rasterization Rendering Processes
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Systems and Methods for Processing a Stream of Data Values Using Data Value Subset Groups
Transformed Geometry Data Cache for Graphics Processing Systems
Buffer Addressing for a Convolutional Neural Network
Memory Interface Having Multiple Snoop Processors
Input/Output Filter Unit for Graphics Processing Unit
Intersection Testing in Ray Tracing Systems with Skipping of Nodes in Sub-trees of Hierarchical Acceleration Structures
Intersection Testing in Ray Tracing Systems Using Hierarchical Acceleration Structures With Implicitly Represented Nodes
Hierarchical Acceleration Structures for Use in Ray Tracing Systems
Intersection Testing in a Ray Tracing System Using Multiple Ray Bundle Intersection Tests
Intersection Testing in a Ray Tracing System Using Ray Bundle Vectors
Method and Graphics Processing System for Rendering One or More Fragments Having Shader-Dependent Properties
Verification of Hardware Design for Data Transformation Pipeline
Methods and Allocators for Allocating Portions of a Storage Unit Using Virtual Partitioning
Multiplexing Between Different Processing Channels
Task Merging
Primitive Processing in a Graphics Processing System
Methods and Systems for Constructing Ray Tracing Acceleration Structures
Methods and Systems for Constructing Ray Tracing Acceleration Structures
Graphics Processing Systems with Expansion Transformation Stage Masks
Processing Primitives Which Have Unresolved Fragments in a Graphics Processing System
Hierarchical Tiling in a Graphics Processing System Using Chain Sorting of Primitives
Hardware Implementation of Convolutional Layer of Deep Neural Network
Methods and Systems for Verifying a Property of an Integrated Circuit Hardware Design Using a Quiescent State
Methods and Systems for Fault Injection Testing of an Integrated Circuit Hardware Design
Task Execution in a Simd Processing Unit with Parallel Groups of Processing Lanes
Neural Network Architecture Using Convolution Engine Filter Weight Buffers
Coarse Depth Test in Graphics Processing Systems
Queues for Inter-Pipeline Data Hazard Avoidance
Evaluating a Mathematical Function in a Computational Environment
Coherency Gathering for Ray Tracing
Scheduling Tasks Using Work Fullness Counter
Texture Filtering with Dynamic Scheduling in Computer Graphics
Primitive Block Generator for Graphics Processing Systems
Anisotropic Texture Filtering for Sampling Points in Screen Space
Ray Tracing System Architectures and Methods
System and Method for Rounding Reciprocal Square Root Results of Input Floating Point Numbers
Task Scheduling in a GPU Using Wakeup Event State Data
Multistage Collector for Outputs in Multiprocessor Systems
Time Stamp Replication Within a Wireless Network Based on Transmission Prediction
Float Division by Constant Integer
Intersection Testing for Ray Tracing
Intersection Testing for Ray Tracing
Intersection Testing for Ray Tracing
Edge Test and Depth Calculation in Graphics Processing Hardware
Building and Scheduling Tasks for Parallel Processing
Verification of Hardware Design for Component That Evaluates an Algebraic Expression Using Decomposition and Recombination
Hidden Culling in Tile-Based Computer Generated Images
Implementation of a Neural Network in Multicore Hardware
Formal Verification Tool to Verify Hardware Design of Memory Unit
Detecting Out-of-Bounds Violations in a Hardware Design Using Formal Verification
Multi-Rendering in Graphics Processing Units Using Render Progression Checks
Tiling a Primitive in a Graphics Processing System by Edge-Specific Testing of a Subset of Tiles in a Rendering Space
Graphics Processing Method and System for Processing Sub-Primitives
Implementation of a Neural Network in Multicore Hardware
Tessellation Method Using Vertex Tessellation Factors
Encoding Images Using Mip Map Compression
Sorting Memory Address Requests for Parallel Memory Access Using Input Address Match Masks
Guaranteed Data Compression Using Reduced Bit Depth Data
Controlling Rendering Operations by Shader Buffer Identification
Apparatus and Method for Processing Floating-Point Numbers
Tile Based Computer Graphics
Gamut Mapping Using Luminance Parameters
Frustum Rendering in Computer Graphics
Workload Repetition Redundancy
Rendering Optimisation by Recompiling Shader Instructions
Method and Apparatus for Rendering a Computer Generated Image
Rendering of Soft Shadows
Intersection Testing in a Ray Tracing System Using Multiple Ray Bundle Intersection Tests
Dedicated Ray Memory for Ray Tracing in Graphics Systems
Guaranteed Data Compression
Systems and Methods for Distributed Scalable Ray Processing
Intersection Testing in a Ray Tracing System Using Ray Bundle Vectors
Accessing Primitive Data Using Tessellated Primitive ID
Atomic Memory Update Unit and Methods
Guaranteed Data Compression
Intersection Testing in Ray Tracing Systems with Skipping of Nodes in Sub-trees of Hierarchical Acceleration Structures
Setting Selection Values for Motion Estimation Vectors Based on Remote Motion Vectors of Interpolated Frames
Conservative Rasterization
Processing Tasks in a Processing System
Determining Anti-Aliasing Settings in Graphics Processing Based on Assessment of Presence of Primitve Edges
Intersection Testing for Ray Tracing
Method and System for Safety Critical Rendering of a Frame
Method and System for Safety Critical Rendering of a Frame
Method and System for Wirelessly Transmitting Data
Encoding and Decoding Variable Length Instructions
Graphics Processing Units and Methods for Controlling Rendering Complexity Using Cost Indications for Sets of Tiles of a Rendering Space
Image Data Decompression Using Difference Values Between Data Values and Origin Values for Image Data Channels
Processing Received Pixel Values in an Image Processing System Using Pixel Value Subset Groups
Tessellation Hardware Subdivision of Patches Into Sub-Patches
Post-Tessellation Blending in a Gpu Pipeline
Rasterising Aliased Lines
Scheduling Tasks Using Targeted Pipelines
Scalable Parallel Tessellation
Guaranteed Data Compression Using Intermediate Compressed Data
Periodic Reset of Graphics Processor Unit in Safety-Critical Graphics Processing System
Noise Enhanced Histograms
Hierarchical Acceleration Structures for Use in Ray Tracing Systems
Multiplexing Between Different Processing Channels
Tessellation Method Using Recursive Sub-Division of Triangles
Error Allocation Format Selection for Hardware Implementation of Deep Neural Network
Intersection Testing in a Ray Tracing System Using Three-Dimensional Axis-Aligned Box
Intersection Testing in a Ray Tracing System Using Scaled Ray Components
Intersection Testing in a Ray Tracing System Using Scaled Minimum and Maximum Culling Distances
Method and Apparatus for Time Synchronisation in Wireless Networks
Buffer Checker for Task Processing Fault Detection
Image Data Compression
Intersection Testing in a Ray Tracing System Using Convex Polygon Edge Parameters
Intersection Testing in a Ray Tracing System Using a Ray Coordinate System
Intersection Testing in a Ray Tracing System Using Ray Coordinate System Basis Vectors
Generation of a Control Stream for a Tile
Look Ahead Normaliser
Intersection Testing in a Ray Tracing System Using Axis-Aligned Box Coordinate Components
TILE REGION PROTECTION USING MULTIPLE GPUs
Determining Dominant Gradient Orientation in Image Processing Using Double-Angle Gradients
Denoising Filter
Ordering of Patch Selection in Tessellation Operations
Random Accessible Image Data Compression
Communication Interface Between Host System and State Machine Using Event Slot Registers
Methods and Decompression Units for Decompressing a Compressed Block of Image Data
Allocation of Resources to Tasks
ASTC Interpolation
Topology Preservation in a Graphics Pipeline by Analyzing a Geometry Shader
Graphics Processing Method and System for Rendering Items of Geometry Based on Their Size
Graphics Processing System and Method of Rendering
Graphics Processing System and Method of Rendering
Mapping Multi-Dimensional Coordinates to a 1D Space
Efficient Convolution Operations
Livelock Recovery Circuit for Detecting Illegal Repetition of an Instruction and Transitioning to a Known State
Tile Assignment to Processing Cores Within a Graphics Processing Unit
Guaranteed Data Compression Using Alternative Lossless and Lossy Compression Techniques
Verifying Processing Logic of a Graphics Processing Unit
Clock Frequency Adjustment For Semi-Conductor Devices
Importance Sampling for Determining a Light Map
Coding Blocks of Pixels
Anisotropic Texture Filtering by Combining Results of Isotropic Filtering at a Plurality of Sampling Points with a Gaussian Filter
Anisotropic Texture Filtering by Combining Isotropic Filtering Results at Each of a Plurality of Sampling Points
Tessellation Method Using Displacement Factors
Coherency Gathering for Ray Tracing
Sparse Rendering in Computer Graphics
Cube Mapping Using Gradients of an Input Block of Fragments
Lossy Data Compression
Primitive Block Generator for Graphics Processing Systems
Methods and Tiling Engines for Tiling Primitives in a Graphics Processing System
Priority Based Arbitration Between Shared Resource Requestors Using Priority Vectors and Binary Decision Tree
Tile-Based Graphics
Verification of Hardware Design for Component That Evaluates an Algebraic Expression Using Decomposition and Recombination
Data Structures, Methods and Tiling Engines for Storing Tiling Information in a Graphics Processing System
Handling Memory Requests
Determining Lighting Information for Rendering a Scene in Computer Graphics Using Illumination Point Sampling
Neural Network Architecture Using Control Logic Determining Convolution Operation Sequence
Frustum Rendering in Computer Graphics
Configuration Check for Safety-Critical Gpu
Methods and Systems for Fault Injection Testing of an Integrated Circuit Hardware Design
Multi-Output Decoder for Texture Decompression
Rendering an Image of a 3-D Scene
Floating Point Adder
3-D Graphics Rendering with Implicit Geometry
Intersection Testing in a Ray Tracing System Using Convex Polygon Edge Parameters
Methods and Systems for Implementing a Convolution Transpose Layer of a Neural Network
Small Multiplier After Initial Approximation for Operations with Increasing Precision
Methods and Systems for Selecting Quantisation Parameters for Deep Neural Networks Using Back-Propagation
Data Structures, Methods and Tiling Engines for Hierarchically Storing Tiling Information in a Graphics Processing System
Tessellation of Patches of Surfaces in a Tile Based Rendering System
Generating Sparse Sample Histograms in Image Processing
Methods and Control Stream Generators for Generating a Control Stream for a Tile Group in a Graphics Processing System
Float Division by Constant Integer
Transformed Geometry Data Cache for Graphics Processing Systems
Verification of Hardware Design for Data Transformation Component
Hardware Implementation of a Convolutional Neural Network
Memory Allocation for 3-D Graphics Rendering
Methods and Systems for Inter-Pipeline Data Hazard Avoidance
Multi-Core Draw Splitting
Directional Cross Hair Search System and Method for Determining a Preferred Motion Vector
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Method and System for Staggered Parallelized Video Decoding
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Memory Management System and Method
Method and System for Staggered Parallelized Video Decoding
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Directional Cross Hair Search System and Method for Determining a Preferred Motion Vector
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Video Non-Buffered Line Memory
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Primitive Processing in a Graphics Processing System
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Asynchronous & Concurrent Ray Tracing and Rasterization Rendering Processes
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Multiple Precision Level Intersection Testing in a Ray Tracing System
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Scheduling Heterogeneous Computation on Multithreaded Processors
Hardware Implementation of a Deep Neural Network with Variable Output Data Format
Accessing Primitive Data Using Tessellated Primitive ID
Selecting an Ith Largest or a Pth Smallest Number from a Set of N M-Bit Numbers
Hardware Implementation of a Neural Network
Analysing Objects in a Set of Frames
Apparatus and Method for Processing Detection Boxes
Methods and Decompression Units for Decompressing Image Data Compressed Using Pattern-Based Compression
Hypervisor Removal
Computing Systems and Methods for Processing Graphics Data Using Cost Indications for Sets of Tiles of a Rendering Space
Livelock Detection in a Hardware Design Using Formal Evaluation Logic
Conservative Rasterization Using Gradients
Intersection Testing in Ray Tracing Systems Using Hierarchical Acceleration Structures With Implicitly Represented Nodes
Executing Functions In Response To Reading Event Indices On An Event Queue By A State Machine
Intersection Testing in a Ray Tracing System Using Convex Polygon Edge Signed Parameters
Tile-Based Scheduling Using Per-Tile Hash Values
Coding Blocks of Pixels
Texture Address Generation Using Fragment Pair Differences
Verifying a Hardware Design for a Multi-Stage Component
Rendering an Image of a 3-D Scene
Processor with Hardware Pipeline
Detecting Error in Safety-Critical Gpu by Monitoring for Response to an Instruction
Histogram-Based Per-Layer Data Format Selection for Hardware Implementation of Deep Neural Network
Guaranteed Data Compression
Compressing and Decompressing Image Data Using Compacted Region Transforms
Tessellation Hardware Subdivision of Patches Into Sub-Patches
Method and Apparatus for Rendering a Computer Generated Image
Scalable Parallel Tessellation
Intersection Testing in a Ray Tracing System Using Multiple Ray Bundle Intersection Tests
Learned Feature Motion Detection
Conservative Rasterization
Rendering Optimisation by Recompiling Shader Instructions
Method and Circuit for Performing Error Detection on a Clock Gated Register Signal
Task Execution in a Simd Processing Unit with Parallel Groups of Processing Lanes
Dedicated Ray Memory for Ray Tracing in Graphics Systems
Verification of Hardware Design for Integrated Circuit Implementing Polynomial Input Variable Function
Detecting Out-of-Bounds Violations in a Hardware Design Using Formal Verification
Systems and Methods for Distributed Scalable Ray Processing
Scheduling Computation Tasks for Execution by Multiple Processing Units Using Computation Task Profiling
Complementary Vectors
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Hierarchical Mantissa Bit Length Selection for Hardware Implementation of Deep Neural Network
Tile Region Protection in a Graphics Processing System
Approximating Functions
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Synchronising Devices Using Clock Signal Delay Comparison
Synchronisation of Execution Threads on a Multi-Threaded Processor
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Safety-Critical Rendering in Graphics Processing Systems
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High Definition Timing Synchronisation Function
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Executing Memory Requests Out of Order
Processing Blocks of Input Data Depthwise Through Layers of a Neural Network
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Multiple Precision Level Intersection Testing in a Ray Tracing System
Object Illumination in Hybrid Rasterization and Ray Traced 3-D Rendering
Gpu Virtualisation
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Pattern-Based Image Data Compression
Efficient Encoding Methods
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Methods and Systems for Selecting Number Formats for Deep Neural Networks Based on Network Sensitivity and Quantisation Error
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Convolutional Neural Network Hardware Configuration
Methods and Systems for Running Dynamic Recurrent Neural Networks in Hardware
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Number Format Selection in Recurrent Neural Networks
Multiple-Input Floating-Point Processing with Mantissa Bit Extension
Methods and Systems for Converting Weights of a Deep Neural Network from a First Number Format to a Second Number Format
Downscaler and Method of Downscaling
Downscaler and Method of Downscaling
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Hardware Implementation of Windowed Operations in Three or More Dimensions
Memory Allocation for Recursive Processing in a Ray Tracing System
Memory Allocation in a Ray Tracing System
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Verification of Hardware Design for an Integrated Circuit That Implements a Function That Is Polynomial in One or More Sub-Functions
Rendering in Computer Graphics Systems
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Assigning Primitives to Tiles in a Graphics Processing System
Interpolating a Sample Position Value by Interpolating Surrounding Interpolated Positions
Rendering a Scene Using a Reduced Memory Representation of a Polynomial Function to Determine an Output Value Approximating a Mathematical Function
Task Assembly for SIMD Processing Using Characteristics of Computation Instance for Allocation to a Task
Hierarchy Merging in Computer Graphics
Data Compression and Packing
Data Decompression and Packing
Compressing a Set of Coefficients for Subsequent Use in a Neural Network
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Implementing Fully-Connected Neural-Network Layers in Hardware
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Neural Network Comprising Matrix Multiplication
Implementing Dilated Convolution in Hardware
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Hardware Unit for Performing Matrix Multiplication with Clock Gating
Training a Neural Network
Task Repacking
Modifying Processing of Commands in a Command Queue Based on Accessed Data Related to a Command
Sampling for Feature Detection in Image Analysis
Method and System for Multisample Antialiasing
Computer System and Method Using a First Page Table and a Second Page Table
Method of Performing Hardware Efficient Unbiased Rounding of a Number
Methods and Systems for Generating the Gradients of a Loss Function with Respect to the Weights of a Convolution Layer
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Performing Comparison Operations Using Vector Floating Point Values
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Performing Constant Modulo Arithmetic
Buffer Addressing for a Convolutional Neural Network
Implementation of Softmax and Exponential in Hardware
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Iterative Estimation Hardware
Untransformed Display Lists in a Tile Based Rendering System
Methods and Systems for Measuring the Security of an Electronic Device Comprising Hardware and Software
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Managing Resources in a Graphics Processing Pipeline by Suspending Tasks at Phase Boundaries
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Implementation of Argmax or Argmin in Hardware
Implementation of Pooling and Unpooling or Reverse Pooling in Hardware
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Neural Network Comprising Matrix Multiplication
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Scheduling Processing in a Ray Tracing System
Systems and Methods for 3-D Scene Acceleration Structure Creation and Updating
Intersection Testing in a Ray Tracing System
Implementing Functions in Hardware
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Transformation of Data in a Ray Tracing System
Hybrid Fixed Logic for Performing Multiplication
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Running Bidirectional Recurrent Neural Networks in Hardware
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Constant Multiplication by Division
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Synchronizing Scheduling Tasks with Atomic Alu
Efficient Convolution Operations with a Kernel Shader
Image Processing Using Filtering Function Covariance
Anisotropic Texture Filtering Using Adaptive Filter Kernel
Allocation of Primitives to Primitive Blocks
Activation Functions for Deep Neural Networks
Texture Filtering of Texture Represented by Multilevel Mipmap
Anisotropic Texture Filtering Using Weights of an Anisotropic Filter That Minimize a Cost Function
Number Format Selection for Bidirectional Recurrent Neural Networks
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Tessellating Patches of Surface Data in Tile Based Computer Graphics Rendering
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Graphics Processor
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Overlapped Geometry Processing in a Multicore Gpu
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Rendering an Image of a 3-D Scene Using Guided Image Filtering
Implementation of Discrete Fourier-Related Transforms in Hardware
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Data Structures, Methods and Primitive Block Generators for Storing Primitives in a Graphics Processing System
Floating Point to Fixed Point Conversion Using Exponent Offset
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Assembling Primitive Data into Multi-View Primitive Blocks in a Graphics Processing System
Hybrid Hierarchy of Bounding and Grid Structures for Ray Tracing
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Excluding Video Frame Blocks from Compensation Based on Difference Determination
On Demand Geometry and Acceleration Structure Creation with Tile Object Lists
Methods and Devices for Configuring a Neural Network Accelerator with a Configurable Pipeline
Application:
17/956,985 →
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US US20230177318A1
Neural Network Accelerator with a Configurable Pipeline
Application:
17/957,089 →
Publication:
US US20230177321A1
Neural Network Accelerator with a Configurable Pipeline
Floating Point to Fixed Point Conversion
Neural Network Architecture Using Convolution Engines
Upscaling Lower Resolution Image Data for Processing
Out-Of-Bounds Recovery Circuit
Neural Network Architecture Using Single Plane Filters
Intersection Testing in a Ray Tracing System Using Scaled Ray Components
Apparatus and Method for Processing Floating-Point Numbers
Application:
18/119,355 →
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US US20230221924A1
Multiplication by a Rational in Hardware with Selectable Rounding Mode
Application:
18/072,463 →
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US US20230229397A1
Truncated Array for Performing Division
Application:
18/072,185 →
Publication:
US US20230229394A1
Graphics Processing System and Method of Rendering
Graphics Processing System and Method of Rendering Combining Shader Fragment Task Instances Associated with Different Fragment Shading Rates into a Shading Task
Application:
18/080,073 →
Publication:
US US20230230308A1
Processing Work Items in Processing Logic
Method and Graphics Processing System for Rendering One or More Fragments Having Shader-Dependent Properties
Application:
18/123,230 →
Publication:
US US20230230319A1
Virtual Camera for 3-D Modeling Applications
Graphics Processor with Non-Blocking Concurrent Architecture
Random Accessible Lossless Parameter Data Compression for Tile Based 3D Computer Graphics Systems
Method of Traversing a Hierarchical Acceleration Structure
Rendering a Scene Using Secondary Ray Tracing
Configurable Pooling Processing Unit for Neural Network Accelerator
Application:
18/092,132 →
Publication:
US US20230259578A1
Neural Network Accelerator with Configurable Pooling Processing Unit
Application:
18/092,095 →
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Building an Acceleration Structure for Use in Ray Tracing
Graphics Processing Systems with Expansion Transformation Stage Masks
Stereoscopic Graphics Processing
Find First Function
Application:
18/115,149 →
Publication:
US US20230280980A1
Building and Scheduling Tasks for Parallel Processing
Allocation of Memory Resources to Simd Workgroups
Application:
18/201,010 →
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Clock Synchronisation Between Devices Using Message Timestamps
Median Value Determination in a Data Processing System
Application:
18/135,715 →
Publication:
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Trailing or Leading Digit Anticipator
Image Data Decompression
Managing Access to Memory by Determining Virtual Addresses in Dependence on Access Request Type
Replicating Logic Blocks to Enable Increased Throughput with Sequential Enabling of Input Register Blocks
Application:
18/207,056 →
Publication:
US US20230325195A1
Controlling Rendering Operations by Shader Buffer Identification
Guaranteed Data Compression Using Reduced Bit Depth Data
Method and System for Calculating Dot Products
Application:
18/111,033 →
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US US20230334117A1
Method and System for Processing Floating Point Numbers
Application:
18/111,178 →
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US US20230333812A1
Intersection Testing in a Ray Tracing System Using Comparison of Intersection Distance Differences Between Primitive Intersections
Intersection Testing in a Ray Tracing System Using Offset Intersection Distances
Intersection Testing in a Ray Tracing System
Method and System for Controlling a Memory Device
Data Compression and Decompression
Application:
18/123,939 →
Publication:
US US20230334708A1
Data Compression and Decompression
Data Compression and Decompression
Control Stream Stitching for Multicore 3-D Graphics Rendering
Application:
18/125,681 →
Publication:
US US20230334748A1
Memory Management for Multicore 3-D Graphics Rendering
Memory Management for Multicore 3-D Graphics Rendering
Memory Management for Multicore 3-D Graphics Rendering
Formation of Bounding Volume Hierarchies
Formation of Bounding Volume Hierarchies
Methods and Hardware Logic for Loading Ray Tracing Data into a Shader Processing Unit of a Graphics Processing Unit
Methods and Hardware Logic for Writing Ray Tracing Data from a Shader Processing Unit of a Graphics Processing Unit
Using Tiling Depth Information in Hidden Surface Removal in a Graphics Processing System
Application:
18/211,530 →
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Systems and Methods for Soft Shadowing in 3-D Rendering Casting Multiple Rays from Ray Origins
Foveated Rendering
Application:
18/211,725 →
Publication:
US US20230334761A1
Tessellation Method Using Vertex Tessellation Factors
Hidden Culling in Tile-Based Computer Generated Images
Geometry to Tiling Arbiter for Tile-Based Rendering System
Graphics Processing Method and System for Rendering Items of Geometry Based on Their Size
Multistage Collector for Outputs in Multiprocessor Systems
Coherency Gathering for Ray Tracing
Graphics Processing Units and Methods for Controlling Rendering Complexity Using Cost Indications for Sets of Tiles of a Rendering Space
Truncated Array for Multiplication by Rational
Application:
18/072,356 →
Publication:
US US20230376275A1
Multicore State Caching in Graphics Processing
Hierarchical Tiling in a Graphics Processing System Using Chain Sorting of Primitives
Application:
18/228,190 →
Publication:
US US20230377092A1
Task Scheduling in a GPU Using Wakeup Event State Data
Application:
18/228,545 →
Publication:
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Anisotropic Texture Filtering for Sampling Points in Screen Space
Multi-Viewport Transformation Module for use in 3D Rendering System
Formation of Bounding Volume Hierarchies
Method and Circuit for Performing Error Detection on a Clock Gated Register Signal
Task Merging
Asynchronous and Concurrent Ray Tracing and Rasterization Rendering Processes
Bilateral Filter with Data Model
ASTC Interpolation
Memory Interface Having Multiple Snoop Processors
Graphics Processing Using Directional Representations of Lighting at Probe Positions Within a Scene
Reducing Redundant Rendering in a Graphics System
Application:
18/129,197 →
Publication:
US US20230401778A1
ASTC Interpolation
Edge Test and Depth Calculation in Graphics Processing Hardware
Graphics Processing Method and System for Rendering Items of Geometry Based on Their Size
Intersection Testing in a Ray Tracing System Using Axis-Aligned Box Coordinate Components
Multicore Master/Slave Communications
Accumulator Hardware
Application:
18/129,019 →
Publication:
US US20230409287A1
Reducing Redundant Rendering in a Graphics System
Intersection Testing in a Ray Tracing System Using Three-Dimensional Axis-Aligned Box
Low Latency Distortion Unit for Head Mounted Displays
Method and Apparatus for Use in the Design and Manufacture of Integrated Circuits
Methods and Systems for Storing Variable Length Data Blocks in Memory
Periodic Reset of Graphics Processor Unit in Safety-Critical Graphics Processing System
Method and System for Wirelessly Transmitting Data
Primitive Processing in a Graphics Processing System
Image Noise Reduction
Intersection Testing in Ray Tracing Systems with Skipping of Nodes in Sub-trees of Hierarchical Acceleration Structures
Scheduling Tasks in a Processor
Rasterising Aliased Lines
Look Ahead Normaliser
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Matching Local Image Feature Descriptors in Image Analysis
Maintaining Synchronisation Between Memory Writing and Reading Blocks Using an Internal Buffer and a Control Channel
Method and System for Verifying a Sorter
Workload Repetition Redundancy
Tiling a Primitive in a Graphics Processing System by Testing Subsets of Tiles in a Rendering Space
Application:
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US US20240037693A1
Methods and Allocators for Allocating Portions of a Storage Unit Using Virtual Partitioning
Topology Preservation in a Graphics Pipeline by Analyzing a Geometry Shader
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18/382,451 →
Publication:
US US20240046545A1
Reduced Acceleration Structures for Ray Tracing Systems
Ray Tracing System Architectures and Methods
Tile Assignment to Processing Cores Within a Graphics Processing Unit
Hierarchical Acceleration Structures for Use in Ray Tracing Systems
Methods and Graphics Processing Units for Determining Differential Data for Rays of a Ray Bundle
Rendering of Soft Shadows
Application:
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US US20240078739A1
Compressed Ray Direction Data in a Ray Tracing System
Application:
18/388,914 →
Publication:
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Guaranteed Data Compression
Decoding Images Compressed Using Mip Map Compression
Sorting Memory Address Requests for Parallel Memory Access Using Input Address Match Masks
Graphics Processing Method and System for Processing Sub-Primitives
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18/513,532 →
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Single Pass Rendering for Head Mounted Displays
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18/515,153 →
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Image Data Compression
Image Data Decompression Using Difference Values Between Data Values and Origin Values for Image Data Channels
Multi-Output Decoder for Texture Decompression
Floating Point Adder
Guaranteed Data Compression
Application:
18/520,101 →
Publication:
US US20240106458A1
Primitive Block Generator for Graphics Processing Systems
Methods and Systems for Performing Channel Equalisation on a Convolution Layer in a Neural Network
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18/375,398 →
Publication:
US US20240111990A1
Priority Based Arbitration
Graphics Processing Systems and Methods
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Mapping Neural Networks to Hardware
Application:
18/212,347 →
Publication:
US US20240119254A1
Processing Fragments Which Have a Shader-Dependent Property in a Graphics Processing System
Controlling Scheduling of a Gpu
Compression and Decompression of Sub-Primitive Presence Indications for Use in a Rendering System
Hardware Implementation of an Attention-Based Neural Network
Application:
18/211,208 →
Publication:
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Hardware Implementation of an Attention-Based Neural Network
Application:
18/211,202 →
Publication:
US US20240127044A1
Verification of a Hardware Design for an Integrated Circuit to Implement a Floating Point Product of Power Functions
Application:
18/216,196 →
Publication:
US US20240126965A1
Ray Tracing Using Indications of Re-Entry Points in a Hierarchical Acceleration Structure
Apparatus and Method for Processing Floating-Point Numbers
TILE REGION PROTECTION USING MULTIPLE GPUs
Implementing Traditional Computer Vision Algorithms as Neural Networks
Application:
18/136,709 →
Publication:
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Processing Data Using a Neural Network Implemented in Hardware
Application:
18/216,383 →
Publication:
US US20240135153A1
Efficient Floating Point Squarer
Application:
18/240,618 →
Publication:
US US20240134602A1
Hardware to Perform Squaring
Application:
18/240,387 →
Publication:
US US20240134607A1
Adaptive Sharpening for Blocks of Pixels
Application:
18/373,710 →
Publication:
US US20240135505A1
Adaptive Sharpening for Blocks of Pixels
Upsampling Blocks of Pixels
Tessellation Method Using Recursive Sub-Division of Triangles
Application:
18/519,632 →
Publication:
US US20240135648A1
Guaranteed Data Compression
Method and Apparatus for Time Synchronisation in Wireless Networks
Patent:
12,395,312 →
Application:
18/401,381 →
Allocation of Memory by Mapping Registers Referenced by Different Instances of a Task to Individual Logical Memories
Application:
18/401,558 →
Publication:
US US20240134572A1
Data Compression and Storage
Application:
18/401,545 →
Publication:
US US20240137044A1
Data Structures, Methods and Tiling Engines for Storing Tiling Information in a Graphics Processing System
Identifying One or More Quantisation Parameters for Quantising Values to Be Processed by a Neural Network
Application:
18/216,461 →
Publication:
US US20240143985A1
Methods and Systems for Executing a Neural Network on a Neural Network Accelerator
Application:
18/216,008 →
Publication:
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Intersection Testing for Ray Tracing
Gamut Mapping Using Luminance Parameters
Ray Tracing Using Compressed Ray Data Representation for a Ray Having Three Direction Components and Three Position Components
Adaptive Sharpening for Blocks of Upsampled Pixels
Application:
18/478,050 →
Publication:
US US20240161253A1
Distributed System Level Cache
Methods and Systems for Online Selection of Number Formats for Network Parameters of a Neural Network
Application:
18/375,198 →
Publication:
US US20240160908A1
Implementing a Scatter Function on a Neural Network Accelerator
Application:
18/385,556 →
Publication:
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Scheduling Tasks Using Work Fullness Counter
Methods and Systems for Performing a Per Channel Affine Transformation Using a Neural Network Accelerator
Application:
18/385,816 →
Publication:
US US20240169191A1
Multi-Rendering in Graphics Processing Units Using Render Progression Checks
Hardware Efficient Rounding
Application:
18/581,261 →
Publication:
US US20240319963A1
Verifying That a Hardware Design for a Component Is Permutation Respecting
Application:
18/375,466 →
Publication:
US US20240176939A1
Implementing a Scatter Function on a Neural Network Accelerator
Application:
18/385,487 →
Publication:
US US20240169024A1
Implementing a Scatter Function on a Neural Network Accelerator
Application:
18/385,690 →
Publication:
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Graphics Processing System and Method of Rendering
Generating an Augmented Reality Image Using a Blending Factor
Image Data Compression
Application:
18/532,311 →
Publication:
US US20240314291A1
Image Data Decompression
Sorting Elements in a Memory Array by Comparing Element Vectors
Sorting
Application:
18/534,595 →
Publication:
US US20240192918A1
Variable Input Shapes at Runtime
Application:
18/538,360 →
Publication:
US US20240232600A1
Hardware Mapping
Application:
18/541,596 →
Publication:
US US20240231845A1
Scheduling of Duplicate Threads
Application:
18/391,326 →
Publication:
US US20240231900A1
Scheduling of Duplicate Threads
Implementing Neural Networks in Hardware
Application:
18/393,320 →
Publication:
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Mapping Neural Networks to Hardware
Application:
18/393,536 →
Publication:
US US20240232597A1
Performing a Separable Operation on a Two-Dimensional Array of Values at a Processing Unit Comprising a Memory
Application:
18/392,228 →
Publication:
US US20240231913A1
Performing an Operation on an Array of Values at a Processing Unit
Applying Texture Processing to a Block of Fragments in a Graphics Processing Unit
Application:
18/394,274 →
Publication:
US US20240273669A1
Applying Texture Processing to a Block of Fragments in a Graphics Processing Unit
Application:
18/394,420 →
Publication:
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Retrieving a Block of Data Items in a Processor
Retrieving a Block of Data Items in a Processor
Application:
18/395,102 →
Publication:
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Controlling Operation of a Gpu
Application:
18/395,942 →
Publication:
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Small Multiplier After Initial Approximation for Operations with Increasing Precision
3-D Graphics Rendering with Implicit Geometry
Tessellation of Patches of Surfaces in a Tile Based Rendering System
Determining Lighting Information for Rendering a Scene in Computer Graphics Using Illumination Point Sampling
Encoding and Decoding Variable Length Instructions
Graphics Processing System and Method of Rendering
Atomic Memory Update Unit and Methods
Intersection Testing for Ray Tracing
Methods and Systems for Implementing a Convolution Transpose Layer of a Neural Network
Sparse Rendering in Computer Graphics
Determining Dominant Gradient Orientation in Image Processing Using Double-Angle Gradients
Methods and Systems for Inter-Pipeline Data Hazard Avoidance
Multi-Core Draw Splitting
Tessellation Method Using Displacement Factors
Decoding a Compressed Data Structure
Application:
18/587,893 →
Publication:
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Denoising Filter
Encoding a Block of Pixels
Application:
18/587,868 →
Publication:
US US20240323404A1
Random Accessible Image Data Compression
Cube Mapping Using Gradients of an Input Block of Fragments
Compressing a Neural Network
Application:
18/589,092 →
Publication:
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Compressing a Neural Network
Application:
18/589,256 →
Publication:
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Checking Data Integrity by Comparing Error-Check Signals Generated on Different Clock Cycles
Flexible Cache Structure for Caching Compressed and Uncompressed Data
Flexible Cache Structure for Caching Compressed and Uncompressed Data
Methods and Systems for Performing a Sparse Submanifold Convolution on a Gpu
Application:
18/591,092 →
Publication:
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Methods and Systems for Performing a Sparse Submanifold Convolution Using an Nna
Application:
18/591,401 →
Publication:
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Methods and Systems for Performing a Sparse Submanifold Deconvolution on a Gpu
Methods and Systems for Performing a Standard Convolution on a Gpu
Application:
18/591,211 →
Publication:
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Methods and Systems for Performing a Standard Deconvolution on a Gpu
Application:
18/591,869 →
Publication:
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Coarse Depth Test in Graphics Processing Systems
Patent:
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Application:
18/594,863 →
Data Structures, Methods and Tiling Engines for Hierarchically Storing Tiling Information in a Graphics Processing System
Patent:
12,367,633 →
Application:
18/594,999 →
Input/Output Filter Unit for Graphics Processing Unit
Methods and Systems for Selecting Quantisation Parameters for Deep Neural Networks Using Back-Propagation
Tile Based Computer Graphics
Patent:
12,406,325 →
Application:
18/594,282 →
Data Compression and Decompression Methods and Systems in Ray Tracing
Application:
18/599,517 →
Publication:
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Tessellation Methods and Systems in Ray Tracing
Application:
18/599,607 →
Publication:
US US20240303905A1
Ordering of Patch Selection in Tessellation Operations
Processing Primitives Which Have Unresolved Fragments in a Graphics Processing System
Memory Allocation for 3-D Graphics Rendering
Processing Tasks in a Processing System
Graphics Processing System and Method of Rendering
System and Method of Performing Convolution Efficiently Adapting Winograd Algorithm
Application:
18/613,443 →
Publication:
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Handling Memory Requests
Rendering Views of a Scene in a Graphics Processing Unit
Verifying Processing Logic of a Graphics Processing Unit
Method and Data Processing System for Resampling a Set of Samples
Application:
18/617,810 →
Publication:
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Training a Machine Learning Algorithm to Perform Motion Estimation of Objects in a Set of Frames
Resource Management
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18/621,597 →
Publication:
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Task Dependencies
Application:
18/621,392 →
Publication:
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Hardware Implementation of a Convolutional Neural Network
Application:
18/623,450 →
Publication:
US US20240249131A1
Multi-Phased and Multi-Threaded Program Execution Based on Simd Ratio
Application:
18/623,181 →
Publication:
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Buffer Checker for Task Processing Fault Detection
Method and System for Safety Critical Rendering of a Frame
Application:
18/628,365 →
Publication:
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Tile-Based Graphics
Application:
18/628,253 →
Publication:
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Generation of a Control Stream for a Tile
Learned Image Transformation Methods and Systems in Graphics Rendering
Anisotropic Texture Filtering by Combining Results of Isotropic Filtering at a Plurality of Sampling Points with a Gaussian Filter
Allocation of Resources to Tasks
Texturing/Shading in a Gpu Pipeline Bypassing Bilinear Filter
Mapping Multi-Dimensional Coordinates to a 1D Space
Post-Tessellation Blending in a Gpu Pipeline
Triangle Pairing Optimizer
Application:
18/668,667 →
Publication:
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Verifying Firmware Binary Images Using a Hardware Design and Formal Assertions
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Publication:
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Anisotropic Texture Filtering Using Weights of an Anisotropic Filter That Minimize a Cost Function
Verification of Hardware Design for Data Transformation Component
Rendering an Image of a 3-D Scene
Scheduling Tasks Using Targeted Pipelines
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18/676,283 →
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Texture Address Generation Using Fragment Pair Differences
Compressing a Neural Network
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Methods and Systems for Performing Ssd Post Processing
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Accessing Primitive Data Using Tessellated Primitive Id
Detecting Error in Safety-Critical Gpu by Monitoring for Response to an Instruction
Common Priority Information for Multiple Resource Arbitration
High Accuracy Texture Filtering in Computer Graphics
Ray Tracing in Computer Graphics Using Intersection Testing at Selective Resolution
Method, Apparatus, and Computer Readable Medium for Light Energy Accounting in Ray Tracing
Related Assignments
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Release of Security Interest
Dec 18, 2012
From: SILICON VALLEY BANK
To: AMBRIC, INC.
Reel/Frame 029489/0598 →
Assignment of Assignor's Interest
Nov 11, 2013
From: NETHRA IMAGING, INC.
To: METAGENCE TECHNOLOGIES LIMITED
Reel/Frame 031576/0320 →
Assignment of Assignor's Interest
Nov 11, 2013
From: METAGENCE TECHNOLOGIES LIMITED
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 031576/0540 →
Assignment of Assignor's Interest
Oct 22, 2015
From: SINGLETON, IAIN; DARBARI, ASHISH; NETTERVILLE, JOHN ALEXANDER OSBORNE
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 036859/0547 →
Assignment of Assignor's Interest
Mar 28, 2017
From: LANDERS, MARK; ROBINSON, MARTIN JOHN
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 041763/0875 →