Granted Patent B2

US 12,412,234 · App. 18/126,286 · Granted Sep 9, 2025

Inventor: Michael John Livesley (Hertfordshire, GB)

Assignee: Imagination Technologies Limited

G06T1/60G06T15/005

Abstract

Claims (47)

1. A multicore graphics rendering system comprising a plurality of cores, configured to implement tile-based rendering of a stream of primitives, wherein:

first cores of the plurality of cores are configured to perform geometry processing work, and second cores of the plurality of cores are configured to perform fragment processing work; and

each first core is configured to process groups of primitives, to produce transformed geometry data describing, for each of a plurality of tiles, the primitives processed by that first core that are present in that tile, each group being associated with a group index, the group indices defining an ordering of the groups in the stream of primitives;

the first cores being configured to store in a memory the transformed geometry data that they produce;

each second core being configured to perform fragment processing for one or more of the tiles, wherein each second core is configured to, for each tile to be processed, read from the memory the transformed geometry data produced by the first cores for that tile;

wherein one of the plurality of cores comprises an allocation manager, configured to allocate portions of the memory to the first cores to store the transformed geometry data;

wherein the second cores are configured to execute a partial render, comprising performing fragment processing for the primitives in a renderable range of groups, the renderable range starting with a starting group and ending with an ending group, wherein, before executing the partial render, the geometry processing work has been completed for every group ahead of the ending group in the ordering defined by the group indices;

wherein the multicore graphics rendering system uses at least one virtualised memory space, wherein each of the plurality of cores comprises a memory management unit (MMU), configured to translate between virtual memory portions in the at least one virtualised memory space and physical memory portions of the memory;

wherein the allocation manager is configured to allocate for the MMUs a hierarchical index to index the physical memory portions associated with the virtual memory portions in the at least one virtualised memory space;

wherein the allocation manager is configured to record the portions of memory allocated to the MMUs for the hierarchical index in an MMU list, (MLIST);

wherein the MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index;

wherein the allocation manager is configured to, after a partial render:

identify, from the MLIST, the portions of memory associated with indexing virtual memory that has been fully consumed by the plurality of second cores performing fragment processing; and

free the identified portions of memory.

2. The graphics rendering system of claim 1 , wherein the allocation manager is configured to, after freeing the identified portions of memory, compact the MLIST, such that MLIST entries corresponding to the freed portions of memory are invalidated, and the remaining MLIST entries are consolidated into a consecutive set of entries.

3. The graphics rendering system of claim 1 , wherein the hierarchical index includes a top level and one or more additional levels, wherein:

the memory for storing the top level of the hierarchical index is allocated statically; and

the memory for storing the one or more additional levels of the hierarchical index is allocated dynamically.

4. The graphics rendering system of claim 1 , wherein the allocation manager is configured to segment the virtualised memory space such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the hierarchical index,

wherein the allocation manager is configured to, before geometry processing for a frame begins, pre-allocate the top level of the hierarchical index, and prime each MMU by providing the MMU with said top level of the hierarchical index.

5. A method for tile-based rendering of a stream of primitives in a multicore graphics rendering system, comprising a plurality of cores, the method comprising:

using first cores of the plurality of cores, performing geometry processing work; and

using second cores of the plurality of cores, performing fragment processing work;

wherein the geometry processing work comprises processing, by each first core, groups of primitives, to produce transformed geometry data describing, for each of a plurality of tiles, the primitives processed by that first core that are present in that tile, each group being associated with a group index, the group indices defining an ordering of the groups in the stream of primitives,

the method further comprising storing, by the first cores, in a memory, the transformed geometry data that they produce;

wherein the fragment processing work comprises, for each second core, performing fragment processing for one or more of the tiles, comprising, for each tile to be processed, reading from the memory the transformed geometry data produced by the first cores for that tile;

the method further comprising:

allocating portions of the memory to the first cores to store the transformed geometry data, and

executing, by the second cores, a partial render, comprising performing fragment processing for the primitives in a renderable range of groups, the renderable range starting with a starting group and ending with an ending group, wherein, before executing the partial render, the geometry processing work has been completed for every group ahead of the ending group in the ordering defined by the group indices;

wherein the multicore graphics rendering system uses at least one virtualised memory space, and the method comprises translating between virtual memory portions in the at least one virtualised memory space and physical memory portions of the memory,

the method further comprising:

allocating a hierarchical index to index the physical memory portions associated with the virtual memory portions in the at least one virtualised memory space, and

recording the portions of memory allocated for the hierarchical index in a memory management unit (MMU) list, (MLIST);

wherein the MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index,

wherein the method comprises, after a partial render:

identifying, from the MLIST, the portions of memory associated with indexing virtual memory that has been fully consumed by the plurality of second cores performing fragment processing; and

freeing the identified portions of memory.

6. The method of claim 5 , further comprising, after freeing the identified portions of memory, compacting the MLIST, such that MLIST entries corresponding to the freed portions of memory are invalidated, and the remaining MLIST entries are consolidated into a consecutive set of entries.

7. The method of claim 5 , wherein the hierarchical index includes a top level and one or more additional levels, wherein:

the memory for storing the top level of the hierarchical index is allocated statically; and

the memory for storing the one or more additional levels of the hierarchical index is allocated dynamically.

8. The method of claim 5 , further comprising segmenting the virtualised memory space such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the hierarchical index, and

before geometry processing for a frame begins, pre-allocating the top level of the hierarchical index, and priming each of the plurality of cores by providing the core with said top level of the hierarchical index.

9. A graphics processing system comprising the multicore graphics rendering system as set forth in claim 1 and the memory.

10. A method of manufacturing the graphics processing system as set forth in claim 9 , comprising inputting an integrated circuit definition dataset to an integrated circuit manufacturing system, which when processed in said integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the graphics processing system.

11. A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the graphics processing system as set forth in claim 9 .

12. An integrated circuit manufacturing system configured to manufacture the graphics processing system as set forth in claim 9 .

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (49)