Partially and fully parallel normaliser
View Patent ↗Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
1. Hardware logic arranged to normalize or renormalize a binary number, the hardware logic comprising:
a zero counter arranged to determine a number of leading or trailing zeros in the binary number; and
normalization logic arranged to perform normalization or renormalization of the binary number;
wherein at least a portion of the normalization logic is arranged to operate independently of the zero counter.
2. Hardware logic according to claim 1 , wherein the at least a portion of the normalization logic is arranged to operate without input from the zero counter.
3. Hardware logic according to claim 1 , wherein all of the normalization logic is arranged to operate independently of the zero counter.
4. Hardware logic according to claim 1 , wherein the at least a portion of the normalization logic comprises a normalizer block arranged to operate independently of the zero counter.
5. Hardware logic according to claim 4 , wherein the normalizer block comprises hardware logic arranged to combine pairs of bits in the binary number according to:
r i j:j =α j ·α j−n+1+i
where:
· represents an AND logic function,
n is a number of bits in the binary number,
j is a bit index associated with each of the n-bits in the binary number,
α j is the j th bit in the binary number, and
i is a bit index associated with each bit r i output by the normalizer block.
6. Hardware logic according to claim 5 , wherein the normalizer block further comprises hardware logic arranged to combine values r i j:j in the form of a tree of logic elements to compute output bits r i n−1:0 based on at least one of:
r i j:k =r i j:t +B j:t r i t−1:k and
r i j:k =( r i j:t +B j:t )( r i j:t +r i t−1:k )
where:
+ represents an OR logic function,
t and k are natural numbers, and
B j:t = α j · α j+1 . . . α t+1 · α t .
7. Hardware logic according to claim 6 , wherein the normalizer block further comprises hardware logic arranged to combine values r i j:j in the form of a tree of logic elements to compute output bits r i n−1:n+1−2 α−h based on at least one of:
r i j:k =r i j:t +B j:t r i t−1:k and
r i j:k =( r i j:t +B j:t )( r i j:t +r i t−1:k )
where:
+ represents an OR logic function,
t and k are natural numbers,
α=└log 2 n┘+1,
the subset of bits received from the zero counter comprises h bits, and
B j:t = α j · α j+1 . . . α t+1 · α t .
8. Hardware logic according to claim 1 , wherein the normalization logic comprises:
a shifter arranged to receive a subset of the bits, starting from a most significant bit, generated by the zero counter and to shift the binary number based on the received bits; and
a normalizer block arranged to receive an output from the shifter and to generate an output comprising a normalised version of the binary number.
9. Hardware logic according to claim 8 , wherein the normalizer block comprises hardware logic arranged to combine pairs of input bits according to:
r i j:j =α′ j ·α′ j−n+1+i
where:
· represents an AND logic function,
n is a number of bits in the binary number,
j is a bit index associated with each of the n-bits in the binary number,
α′ j is the j th bit in the number output by the shifter, and
i is a bit index associated with each bit r i output by the normalizer block.
10. A method of normalizing or renormalizing a binary number, the method comprising:
determining, by hardware logic a number of leading or trailing zeros in the binary number in a zero counter; and
normalizing or renormalizing the binary number in normalization logic, and wherein at least a portion of the normalization logic is arranged to operate independently of the zero counter.
11. The method according to claim 10 , wherein the at least a portion of the normalization logic is arranged to operate without input from the zero counter.
12. The method according to claim 10 , wherein all of the normalization logic is arranged to operate independently of the zero counter.
13. A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to
determine a number of leading or trailing zeros in a binary number in a zero counter; and
normalizing or renormalizing the binary number, wherein at least a portion of the normalization or renormalization is performed independently of the zero counter.
14. The non-transitory computer readable storage medium according to claim 13 , wherein at least a portion of the normalization or renormalization operation is performed without input from the zero counter.
15. The non-transitory computer readable storage medium according to claim 13 , wherein all of the normalization or renormalization is performed independently of the zero counter.
16. A non-transitory computer readable storage medium having stored thereon computer executable program code that, when executed at a computer system for generating a representation of a digital circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate hardware logic arranged to normalise or renormalize a binary number, the hardware logic comprising:
a zero counter arranged to determine a number of leading or trailing zeros in the binary number; and
normalization logic arranged to perform normalization or renormalization of the binary number,
wherein at least a portion of the normalization logic is arranged to operate independently of the zero counter.
17. The non-transitory computer readable storage medium according to claim 16 , wherein the at least a portion of the normalization logic is arranged to operate without input from the zero counter.
18. The non-transitory computer readable storage medium according to claim 16 , wherein all of the normalization logic is arranged to operate independently of the zero counter.