SCHEDULING OF DUPLICATE THREADS
A processing system includes safety thread scheduling circuitry which schedules a check thread, being a duplicate of a critical thread, to be executed on a second of a plurality of parallel execution units other than a first execution unit upon which the critical thread is run. The processor further includes comparison circuitry which will compare a result of the critical thread with a result of the check thread, and raise error signal if the results do not match. The safety thread scheduling circuitry is configured to detect when one of the execution units is idle, and if none of the execution units is detected to be idle by the expiry of a safety time-window, to interrupt a non-critical thread executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to execute the check thread in place of the interrupted thread.
1 . A processing system, comprising:
a plurality of parallel execution units each operable to execute a respective series of threads, wherein at least some of the threads executed by at least some of the execution units are non-critical threads not being designated as critical;
request buffering storage operable to receive a request indicating that one of the threads in the respective series executed by a first one of the execution units is designated as a critical thread;
safety thread scheduling circuitry arranged to read the request from the request buffering storage, and in response to schedule a check thread, being a duplicate of the critical thread, to be executed on a second one of the plurality of execution units other than the first execution unit;
result buffering storage arranged to buffer one of: a first result being a result of the execution of the critical thread on the first execution unit, and a second result being a result of the execution of the check thread on the second execution unit; and
comparison circuitry arranged to compare said one of the first and second results from the result buffering storage with the other of the first and second results, and to raise error signal if the first and second results do not match according to said comparison;
wherein the request includes an indication of a safety time-window; and
wherein the safety thread scheduling circuitry is configured to detect when at least one of the execution units is idle, and if none of the execution units is detected to be idle by the expiry of the safety time-window, to interrupt one of the non-critical threads executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to execute the check thread in place of the interrupted thread.
2 . The processing system of claim 1 , wherein the safety thread scheduling circuitry is configured so as: if one of the execution units is detected to be idle upon the reading of the request from the request buffering storage to thereupon select an idle one of the execution units as the second execution unit to begin the execution of the check thread; but if none of the execution units is detected to be idle upon the reading of the request, to wait and detect whether one becomes newly idle before the expiry of the safety time-window and if so thereupon select the newly idle execution unit as the second execution unit to begin the execution of the check thread; but if none becomes idle by the expiry of the safety time-window, to perform said interruption of one of the non-critical threads executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to begin the execution of the check thread in place of the interrupted non-idle thread.
3 . The processing system of claim 2 , wherein the safety thread scheduling circuitry is configured so as to allow the check thread to be interrupted if executed eagerly, being executed eagerly if the execution of the check thread begins being executed before the expiry of the safety time-window; the interruption of the check thread comprising scheduling one or more further critical or non-critical threads to be executed on the second execution unit in place of the check thread.
4 . The processing system of claim 3 , wherein the safety thread scheduling circuitry is configured so as, if the one or more further threads have not completed by expiry of a re-scheduling time limit, to interrupt one of the one or more further threads by resuming the execution of the check thread on the second execution unit, but otherwise to resume execution of the check thread following the completion of the one or more further threads; the re-scheduling time limit being either:
a) the expiry of safety time-window,
b) the expiry of the safety time-window plus any time already spent executing the check thread, or
c) a time in between a) and b).
5 . The processing system of claim 3 , wherein the safety thread scheduling circuitry is configured so as, when the eagerly executed check thread is interrupted by the further thread, to migrate the eagerly executed check thread to another of the execution units other than the first and second execution units.
6 . The processing system of claim 2 , wherein the safety thread scheduling circuitry is configured to raise a panic condition if none of the execution units becomes idle nor is found to be executing a non-critical thread before the expiry of the safety time-window.
7 . The processing system of claim 1 , wherein the first result comprises an indication of memory accesses performed by the critical thread and the second result comprises an indication of memory accesses performed by the check thread.
8 . The processing system of claim 1 , wherein the first and second results are output and compared in compressed form.
9 . The processing system of claim 1 , configured so as to, in response to the error signal:
A) output a warning through a user interface, or
B) disable the first and/or second execution units but continue executing threads on at least one remaining of the execution units, or
C) halt execution across the whole processing system, or
D) execute the critical thread and check thread again at least once on the same or different ones of the execution units and repeat the comparison each time, then perform one of A-C if the repeated comparison still raises the error signal.
10 . The processing system of claim 1 , wherein:
the request buffering storage is operable to buffer multiple requests, each indicating that a respective one of the threads executed on a respective first one of the execution units is to be classed as a critical thread, wherein each request includes an indication of a respective safety time-window;
the thread scheduling circuitry is configured to schedule a respective check thread to be executed on a respective second one of the execution units other than the respective first execution unit, the respective check thread being a duplicate of the respective critical thread;
the result buffering storage is arranged to buffer at least a respective first result of each respective critical thread, or a respective second result of each respective check thread;
the comparison circuitry is configured to compare each second result with the respective first result and raise an error signal if the respective second result doesn't match the respective first result; and
the safety thread scheduling circuitry is configured to schedule the check threads in order of priority wherein the priority is determined according to how close the respective safety time-window is to expiry.
11 . The processing system of claim 10 , wherein the result buffering storage comprises a respective memory access queue for each of the plurality of execution units, and each memory access queue comprises multiple FIFOs for buffering the results of different threads executed on the same execution unit.
12 . The processing system of claim 1 wherein the processing system is embodied in hardware on an integrated circuit.
13 . A method of manufacturing, using an integrated circuit manufacturing system, a processing system as set forth in claim 1 , comprising inputting an integrated circuit definition dataset to said integrated circuit manufacturing system, so as to configure the integrated circuit manufacturing system to manufacture said processing system.
14 . A non-transitory computer readable storage medium having stored thereon a computer readable dataset description that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a processing system comprising:
a plurality of parallel execution units each operable to execute a respective series of threads, wherein at least some of the threads executed by at least some of the execution units are non-critical threads not being designated as critical;
request buffering storage operable to receive a request indicating that one of the threads in the respective series executed by a first one of the execution units is designated as a critical thread;
safety thread scheduling circuitry arranged to read the request from the request buffering storage, and in response to schedule a check thread, being a duplicate of the critical thread, to be executed on a second one of the plurality of execution units other than the first execution unit;
result buffering storage arranged to buffer one of: a first result being a result of the execution of the critical thread on the first execution unit, and a second result being a result of the execution of the check thread on the second execution unit; and
comparison circuitry arranged to compare said one of the first and second results from the result buffering storage with the other of the first and second results, and to raise error signal if the first and second results do not match according to said comparison;
wherein the request includes an indication of a safety time-window; and
wherein the safety thread scheduling circuitry is configured to detect when at least one of the execution units is idle, and if none of the execution units is detected to be idle by the expiry of the safety time-window, to interrupt one of the non-critical threads executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to execute the check thread in place of the interrupted thread.
15 . An integrated circuit manufacturing system configured to manufacture a processing system as set forth in claim 1 .
16 . A method comprising:
scheduling a respective series of threads to execute on each of a plurality of parallel execution units, wherein at least some of the threads executed by at least some of the execution units are non-critical threads not being designated as critical;
receiving a request indicating that one of the threads in the respective series executed by a first one of the execution units is designated as a critical thread;
scheduling a check thread in response to the request, the check thread being a duplicate of the critical thread, to be executed on a second one of the plurality of execution units other than the first execution unit;
buffering one of: a first result being a result of the execution of the critical thread on the first execution unit, and a second result being a result of the execution of the check thread on the second execution unit;
comparing a first result with a second result, the first result being a result of the execution of the critical thread on the first execution unit, and the second result being a result of the execution of the check thread on the second execution unit; and
detecting whether the first and second results match according to said comparison;
wherein the request includes an indication of a safety time-window; and
wherein the method further comprises detecting when at least one of the execution units is idle, and upon none of the execution units being detected to be idle by the expiry of the safety time-window, interrupting one of the non-critical threads executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to execute the check thread in place of the interrupted thread.
17 . A graphics processing system configured to perform the method of claim 16 .
18 . A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method of claim 17 to be performed when run.