Scheduling tasks using work fullness counter

1. A method of scheduling instructions within a parallel processing unit comprising:

decoding, in an instruction controller, an instruction in a scheduled task in an active state;

checking if an Arithmetic Logic Unit (ALU) targeted by the decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU;

in response to determining that the targeted ALU is not full, sending the decoded instruction to the targeted ALU for execution and updating the ALU work fullness counter associated with the targeted ALU;

in response to determining that the targeted ALU is full, triggering a scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state;

monitoring the ALU work fullness counters stored in the instruction controller; and

in response to detecting, as a consequence of the monitoring, that an ALU has changed from being full to not being full, triggering the scheduler to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

2. The method according to claim 1 , further comprising:

checking if a flag in the decoded instruction is set prior to checking if the ALU targeted by the decoded instruction is full; and

in response to determining that the flag in the decoded instruction is set, omitting the checking if the ALU targeted by the decoded instruction is full and sending the decoded instruction to the targeted ALU for execution without updating the ALU work fullness counter associated with the targeted ALU.

3. The method according to claim 1 , wherein checking if an ALU targeted by a decoded instruction from a scheduled task in an active state is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU comprises:

checking, in the instruction controller, if an ALU targeted by a decoded instruction from a scheduled task in an active state is full by checking a value of both an ALU work fullness counter and a de-activated scheduled tasks counter stored in the instruction controller and associated with the targeted ALU;

and wherein the method further comprises:

in response to determining that the targeted ALU is full, updating the de-activated scheduled tasks counter associated with the targeted ALU; and

after triggering the scheduler to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the waiting state, updating the de-activated scheduled tasks counter associated with the ALU.

4. The method according to claim 1 , further comprising:

in response to detecting that an instruction has been removed from a queue in a particular ALU, updating the value of the ALU work fullness counter stored in the instruction controller and associated with the particular ALU.

5. An instruction controller comprising:

an input for receiving an instruction in a scheduled task in an active state from a scheduled task scheduler;

an instruction decoder arranged to decode the received instruction;

a memory element arranged to store a plurality of Arithmetic Logic Unit (ALU) work fullness counters; and

hardware logic arranged to check if an ALU targeted by the decoded instruction is full by checking a value of the ALU work fullness counter associated with the targeted ALU, and in response to determining that the targeted ALU is not full, to send the decoded instruction to the targeted ALU for execution and update the ALU work fullness counter associated with the targeted ALU;

hardware logic arranged, in response to determining that the targeted ALU is full, to trigger the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state; and

hardware logic arranged, to monitor the ALU work fullness counters and in response to detecting, as a consequence of the monitoring, that an ALU has changed from being full to not being full, to trigger the scheduler to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

6. The instruction controller according to claim 5 , further comprising:

hardware logic arranged to check if a flag in the decoded instruction is set prior to checking if the ALU targeted by the decoded instruction is full; and in response to determining that the flag in the decoded instruction is set, to omit the checking if the ALU targeted by the decoded instruction is full and to send the decoded instruction to the targeted ALU for execution without updating the ALU work fullness counter associated with the targeted ALU.

7. The instruction controller according to claim 5 , further comprising:

one or more de-activated scheduled tasks counters; and

hardware logic arranged to check if an ALU targeted by a decoded instruction from a scheduled task in an active state is full by checking if an ALU targeted by a decoded instruction from a scheduled task in an active state is full by checking a value of both an ALU work fullness counter and a de-activated scheduled tasks counter associated with the targeted ALU; and

hardware logic arranged in response to determining that the targeted ALU is full, to update the de-activated scheduled tasks counter associated with the targeted ALU; and after triggering the scheduler to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the waiting state, to update the de-activated scheduled tasks counter associated with the ALU.

8. The instruction controller according to claim 5 , further comprising:

hardware logic arranged, in response to detecting that an instruction has been removed from a queue in a particular ALU, to update the value of the ALU work fullness counter associated with the particular ALU.

9. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller comprising:

an input for receiving an instruction in a scheduled task in an active state from a scheduled task scheduler;

an instruction decoder arranged to decode the received instruction;

a memory element arranged to store a plurality of Arithmetic Logic Unit (ALU) work fullness counters; and

hardware logic arranged to check if an ALU targeted by the decoded instruction is full by checking a value of the ALU work fullness counter associated with the targeted ALU, and in response to determining that the targeted ALU is not full, to send the decoded instruction to the targeted ALU for execution and update the ALU work fullness counter associated with the targeted ALU;

hardware logic arranged, in response to determining that the targeted ALU is full, to trigger the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state; and

hardware logic arranged, to monitor the ALU work fullness counters and in response to detecting, as a consequence of the monitoring, that an ALU has changed from being full to not being full, to trigger the scheduler to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.