Guaranteed data compression

1. A method of converting 10-bit pixel data into 8-bit pixel data, comprising:

determining whether an MSB of any of red, green or blue channel values is equal to one;

in response to determining that no MSB is equal to one, truncating each of the red, green and blue channel values by removing the MSB and LSB from each value; and

appending a flag value to an alpha channel value.

2. The method of claim 1 , wherein the 10-bit pixel data comprises RGBX10:10:10:2 format pixel data.

3. The method of claim 1 , wherein the 8-bit pixel data comprises RGBX8888 format pixel data.

4. A method of compressing 10-bit pixel data comprising:

converting the 10-bit pixel data into 8-bit pixel data according to the method of claim 2 ; and

compressing the RGBX data using a lossy compression technique.

5. The method according to claim 4 , wherein compressing the RGBX data using a lossy compression technique comprises:

dividing a block of pixels into a plurality of sub-blocks; and

for each sub-block:

analysing an alpha channel value for each pixel in the sub-block to select a lossy compression mode from a set of candidate lossy compression modes, wherein the set of candidate lossy compression modes comprises three compression modes which each use a different fixed alpha channel value for all pixels in the sub-block, and

compressing the sub-block using the selected lossy compression mode.

6. The method according to claim 5 , wherein the set of candidate lossy compression modes further comprises one compression mode which uses a variable alpha value for each pixel.

7. The method according to claim 6 , wherein the three compression modes which each use a different fixed alpha channel value for all pixels in the sub-block correspond to three non-zero constant alpha values and wherein the compression mode which uses a variable alpha value is used for a constant alpha value of zero.

8. Hardware logic arranged to convert 10-bit pixel data into 8-bit pixel data, comprising:

determining logic arranged to determine whether an MSB of any of red, green or blue channel values is equal to one;

hardware logic arranged in response to determining that no MSB is equal to one, to truncate each of the red, green and blue channel values by removing the MSB and LSB from each value; and

appending logic arranged to append a flag value to an alpha channel value.

9. A data compression unit comprising:

hardware logic as set forth in claim 8 ; and

a data compression element arranged to compress the 8-bit pixel data output by the hardware logic using a lossy compression technique.

10. Hardware logic configured to perform the method as set forth in claim 1 .

11. The hardware logic of claim 10 , wherein the hardware logic is embodied on an integrated circuit.

12. A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method of claim 1 to be performed when the code is run on a processor.

13. An integrated circuit manufacturing system configured to manufacture hardware logic as claimed in claim 10 .

14. A method of decompressing pixel data, wherein the compressed pixel data is 10-bit pixel data and the decompressed pixel data is 8-bit pixel data, the method comprising:

removing a flag bit from an alpha channel value; and

in response to the flag bit having a first value, adding a leading bit and a trailing bit to each of red, green and blue channel values, wherein each leading bit is a zero.

15. The method of claim 14 , further comprising in response to the flag bit having a second value, converting each of the red, green, and blue channel values from 8-bits to 10-bits.

16. Hardware logic configured to perform the method of claim 14 .

17. The hardware logic of claim 16 , wherein the hardware logic is embodied in hardware on an integrated circuit.

18. A non-transitory computer readable storage medium having stored thereon the computer readable code configured to cause the method as set forth in claim 14 to be performed when the code is run on a processor.

19. An integrated circuit manufacturing system configured to manufacture hardware logic as claimed in claim 16 .