IP Library Granted Patent US 11,531,545
Granted Patent B2
US 11,531,545 · App. 17/108,389 · Granted Dec 20, 2022

Scheduling tasks using swap flags

Inventors: Simon Nield (Kings Langley, GB); Yoong-Chert Foo (Kings Langley, GB); Adam de Grasse (Kings Langley, GB); Luca Iuliano (Kings Langley, GB)
Assignee: Imagination Technologies Limited
G06F9/3016G06F7/575G06F9/3001G06F9/3009G06F9/30185G06F9/3836G06F9/3851G06F9/3867G06F9/522
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Quick Facts
Patent No.
US 11,531,545
App. No.
17/108,389
Granted
Dec 20, 2022
Kind
B2
Abstract

A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.

Claims (15)

1. A method of scheduling instructions within a processing unit comprising:

decoding, in an instruction decoder, an instruction in a scheduled task in an active state; and

in response to determining that a swap flag in the decoded instruction is set, triggering a scheduler to de-activate the scheduled task to a ready state so that it can be activated again at a later time.

2. The method according to claim 1 , further comprising:

in response to determining that the swap flag in the decoded instruction is not set, sending the decoded instruction to an ALU targeted by the decoded instruction.

3. An instruction controller comprising:

an input for receiving an instruction in a scheduled task in an active state from a scheduler;

an instruction decoder arranged to decode the received instruction; and

hardware logic arranged in response to determining that a swap flag in the decoded instruction is set, to trigger the scheduler to de-activate the scheduled task.

4. The instruction controller according to claim 3 , further comprising:

hardware logic arranged in response to determining that the swap flag in the decoded instruction is not set, to send the decoded instruction to an ALU targeted by the decoded instruction.

5. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller comprising:

an input for receiving an instruction in a scheduled task in an active state from a scheduler;

an instruction decoder arranged to decode the received instruction; and

hardware logic arranged in response to determining that the swap flag in the decoded instruction is set, to trigger the scheduler to de-activate the scheduled task to a ready state so that it can be activated again at a later time.

Assignments (1)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →
Priority Claims (1)
GB 1709654 · Jun 16, 2017 · national
Continuity (2)
Continuation 16010935 · Jun 18, 2018
Related Publication 20210081199A1 · Mar 18, 2021