Scheduling tasks using swap flags
A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
1. A method of scheduling instructions within a parallel processing unit comprising:
decoding, in an instruction decoder, an instruction in a scheduled task in an active state;
checking, by an instruction controller, if a swap flag is set in the decoded instruction; and
in response to determining that the swap flag in the decoded instruction is set, triggering a scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
2. The method according to claim 1 , further comprising:
in response to determining that the swap flag in the decoded instruction is not set, sending the decoded instruction to an ALU targeted by the decoded instruction.
3. An instruction controller comprising:
an input for receiving an instruction in a scheduled task in an active state from a scheduler;
an instruction decoder arranged to decode the received instruction; and
hardware logic arranged to check if a swap flag is set in the decoded instruction and in response to determining that the swap flag in the decoded instruction is set, to trigger the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
4. The instruction controller according to claim 3 , further comprising:
hardware logic arranged in response to determining that the swap flag in the decoded instruction is not set, to send the decoded instruction to an ALU targeted by the decoded instruction.
5. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller comprising:
an input for receiving an instruction in a scheduled task in an active state from a scheduler;
an instruction decoder arranged to decode the received instruction; and
hardware logic arranged to check if a swap flag is set in the decoded instruction and in response to determining that the swap flag in the decoded instruction is set, to trigger the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.