IP Library Granted Patent US 8,498,334
Granted Patent B1
US 8,498,334 · App. 12/699,799 · Granted Jul 30, 2013

Method and system for staggered parallelized video decoding

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Quick Facts
Patent No.
US 8,498,334
App. No.
12/699,799
Granted
Jul 30, 2013
Kind
B1
Abstract

A method and system for staggered parallelized video decoding system decodes a compressed video stream at approximately double the performance of conventional systems, and outputs the decoded stream to a video display device. Even and odd video frames from the video stream are identified and stored in a memory. A first decoder processes a first portion of a first even frame from among the stored even frames. After the first decoder completes processing the first portion of the first even frame, a second decoder begins processing a first odd frame from among the stored odd frames. The processing start times of the odd frames are staggered with respect to the even frames and vice versa, and the even and odd frames are simultaneously processed using first and second decoders.

Claims (64)

1. A method for processing video frames, comprising:

receiving a compressed video stream;

identifying even frames and odd frames from the video stream;

storing the even and odd frames in a hardware memory;

processing a first portion of a first even frame from among the stored even frames using a first decoder, the first portion of the first even frame associated with a number of lines of a reference area determined using a search range; and

after the first decoder completes processing the first portion of the first even frame, beginning processing a first odd frame from among the stored odd frames using a second decoder;

wherein the reference area is bounded by a rectangle starting at a location (x−the search range, y−the search range), and ending at a location (x+the search range, y+the search range); and wherein

x and y correspond to coordinates of an upper left corner of a macroblock of the first odd frame decodable by the second decoder.

2. The method for processing video frames of claim 1 , further comprising:

staggering the beginning processing times of the even and odd frames; and

decoding at least some of the even and odd frames simultaneously using the first and second decoders.

3. The method for processing video frames of claim 1 , wherein beginning processing the first odd frame further comprises beginning processing the first odd frame before the first decoder completes processing a remaining portion of the first even frame, the remaining portion being different from the first portion.

4. The method for processing video frames of claim 1 , wherein each of the first and second decoders comprises an H.264 compliant decoder.

5. A method for processing video frames, comprising:

receiving a compressed video stream;

identifying even frames and odd frames from the video stream;

storing the even and odd frames in a hardware memory;

processing a first portion of a first even frame from among the stored even frames using a first decoder;

after the first decoder completes processing the first portion of the first even frame, beginning processing a first odd frame from among the stored odd frames using a second decoder;

processing a first portion of a second even frame from among the stored even frames using the first decoder; and

after the first decoder completes processing the first portion of the second even frame, the second decoder beginning processing a second odd frame from among the stored odd frames;

wherein the first portions of the first and second even frames are associated with a number of lines of a reference area determined using a search range;

the reference area is bounded by a rectangle starting at a location (x−the search range, y−the search range), and ending at a location (x+the search range, y+the search range); and

x and y correspond to coordinates of an upper left corner of a macroblock of at least one of the first and second odd frames.

6. The method of claim 5 , wherein:

processing the first portion of the second even frame occurs after the first decoder processes the first portion of the first even frame; and

beginning processing the second odd frame occurs after beginning processing the first odd frame.

7. The method for processing video frames of claim 1 , wherein the decoding of any video frame is ahead of a next video frame by a processing time that is determined based on at least the number of lines of the reference area.

8. The method of claim 7 , further comprising the first decoder processing each of the even frames ahead of a next odd frame by the processing time.

9. The method of claim 7 , further comprising the second decoder processing each of the odd frames ahead of a next even frame by the processing time.

10. The method for processing video frames of claim 1 , further comprising:

outputting the processed video frames to one or more display devices.

11. A method for processing video frames, comprising:

receiving a compressed video stream;

identifying even frames and odd frames from the video stream;

storing the even and odd frames in a hardware memory;

processing a first portion of a first even frame from among the stored even frames using a first decoder;

after the first decoder completes processing the first portion of the first even frame, beginning processing a first odd frame from among the stored odd frames using a second decoder

determining a frame height H of video frames from the video stream;

dividing the frame height H by a number of lines L associated with a reference area determined using a search range to arrive at a number Z;

rounding down the number Z to a nearest whole number R; and

configuring R or fewer decoders to process at least some of video frames simultaneously.

12. The method of claim 11 , further comprising:

determining G groups of video frames and associating each group with a corresponding one of the R or fewer decoders.

13. The method for processing video frames of claim 11 , further comprising:

simultaneously decoding at least some of the video frames using the R or fewer decoders.

14. The method for processing video frames of claim 13 , wherein simultaneously decoding includes staggering a beginning processing time of each of the R or fewer decoders.

15. The method for processing video frames of claim 1 , wherein identifying the even frames and the odd frames from the video stream includes parsing start codes of at least some of the even frames and the odd frames.

16. A system, comprising:

a parser structured to receive a compressed video stream and to identify groups of video frames from the video stream;

a memory to store the groups of video frames; and

a plurality of video decoders, each decoder structured to process video frames from a corresponding one group of video frames, wherein the beginning processing times for each decoder is staggered;

wherein the number of video decoders in the plurality corresponds to a number no greater than R, wherein R corresponds to a frame height H of at least one of the video frames divided by a number of lines L associated with a reference area, and rounded down to a nearest whole number.

17. The system of claim 16 , wherein the video decoders are structured to simultaneously decode at least one video frame from each group.

18. The system of claim 16 , wherein the decoding of any video frame is ahead of a next video frame by a predefined processing time.

19. The system of claim 16 , wherein the plurality of video decoders corresponds to two decoders and the groups of video frames correspond to a first group having even video frames and a second group having odd video frames.

20. The method for processing video frames of claim 16 , wherein:

the reference area is bounded by a rectangle starting at a location (x−a search range, y−the search range), and ending at a location (x+the search range, y+the search range); and

x and y correspond to coordinates of a corner of a video macroblock.

21. The system of claim 16 , further comprising:

a buffer management unit to store information about decoded video frames from among the groups of video frames; and

one or more monitors to display at least one decoded video frame.

22. The system of claim 21 , wherein at least some of the video decoders are configured to read at least some of the information stored in the buffer management unit about video frames decoded by a different video decoder from among the plurality of video decoders.

23. The system of claim 16 , wherein the parser is configured to identify the groups of video frames based at least on start codes embedded in one or more of the video frames.

Assignments (4)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2013
From: NETHRA IMAGING, INC.
To: METAGENCE TECHNOLOGIES LIMITED
Reel/Frame 031576/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2013
From: METAGENCE TECHNOLOGIES LIMITED
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 031576/0540 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2010
From: CHOUDHARY, SAIF
To: NETHRA IMAGING, INC.
Reel/Frame 023895/0065 →