IP Library Granted Patent US 12,354,208
Granted Patent B2
US 12,354,208 · App. 18/426,221 · Granted Jul 8, 2025

Multi-rendering in graphics processing units using render progression checks

Inventors: John Howson (St. Albans, GB); Steven Fishwick (Kings Langley, GB)
Assignee: Imagination Technologies Limited
G06T15/005G06F5/06G06F9/4881G06T1/20
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Quick Facts
Patent No.
US 12,354,208
App. No.
18/426,221
Granted
Jul 8, 2025
Kind
B2
Abstract

A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.

Claims (26)

1. A graphics processing unit comprising progress check logic configured to: in response to a processor core of the graphics processing unit requesting access to a region of a memory resource to output data as part of a second render, at a time the graphics processing unit has not completed processing a first render, enable that processor core to access that region of the resource if processing for the first render has been completed for that region.

2. The graphics processing unit as claimed in claim 1 , wherein the graphics processing unit further comprises progress indication logic configured to maintain a progress indication indicating progress of the first render, the progress indication indicating regions of the memory resource for which processing for the first render has been completed.

3. The graphics processing unit as claimed in claim 2 , wherein the graphics processing unit further comprises scheduling logic configured to:

allocate rendering tasks to the processor groups for processing to perform the first render; and

at a time when at least one of the processor groups has not completed processing its allocated task(s) as part of the first render, allocating at least one rendering task for the second render to at least one of the other processor groups for processing.

4. The graphics processing unit as claimed in claim 2 , wherein the progress indication logic of the graphics processing unit is configured to update the progress indication in accordance with an update scheme as the first render progresses.

5. The graphics processing unit as claimed in claim 4 , wherein the progress check logic is configured to re-check the progress indication each time the progress indication is updated.

6. The graphics processing unit as claimed in claim 2 , wherein the progress indication logic of the graphics processing unit identifies regions of the memory resource for which processing of rendering tasks for the first render has been completed.

7. The graphics processing unit as claimed in claim 2 , wherein the progress indication of the graphics processing unit comprises a set of flags corresponding to each region of the memory resource, and the progress indication logic is configured to set the flag associated with a region of the memory resource when processing for the first render has completed for that region.

8. The graphics processing unit as claimed in claim 2 , wherein the progress check logic is configured to deny the processor core access to the region of the memory resource in response to the progress indication indicating that processing for the first render has not been completed for that region.

9. The graphics processing unit as claimed in claim 1 , wherein the graphics processing unit comprises multiple processor groups each formed of one or more processor cores and each configured to render graphics data by processing allocated rendering tasks, wherein data for processed rendering tasks is output to regions of the memory resource.

10. The graphics processing unit as claimed in claim 9 , wherein each group of one or more processor cores of the graphics processing unit contains only a single processor core.

11. The graphics processing unit as claimed in claim 9 , wherein each group of one or more processor cores of the graphics processing unit contains a plurality of processor cores.

12. The graphics processing unit as claimed in claim 11 , wherein each of the plurality of processor cores within a group shares a common processing resource of the graphics processing unit.

13. The graphics processing unit as claimed in claim 1 , wherein the processing for the first render has not completed for a region of the memory resource when data stored in that region is modifiable by part of the first render yet to have been completed.

14. The graphics processing unit as claimed in claim 1 , wherein the processing for the first render has completed for a region of the memory resource when data stored in that region is no longer modifiable by the first render.

15. The graphics processing unit as claimed in claim 1 , wherein the graphics data is three-dimensional data and the processor core is configured to process allocated rendering tasks as part of the first render to generate rendered values for voxels, and each region of the memory resource stores data for one or more voxels.

16. The graphics processing unit as claimed in claim 1 , wherein the graphics processing unit is embodied in hardware on an integrated circuit.

17. A method of processing graphics data in a graphics processing unit comprising progress check logic, the method comprising:

in response to a processor core of the graphics processing unit requesting access to a region of a memory resource to output data as part of a second render, at a time the graphics processing unit has not completed processing a first render, enabling that processor core to access to that region of the resource if processing for the first render has been completed for that region.

18. The method as claimed in claim 17 , further comprising maintaining a progress indication indicating progress of the first render, the progress indication indicating regions of the memory resource for which processing for the first render has been completed.

19. The method as claimed in claim 18 , further comprising:

updating the progress indication of the graphics processing unit in accordance with an update scheme as the first render progresses; and

re-checking the progress indication each time the progress indication is updated.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing unit configured to process graphics data, the graphics processing unit comprising progress check logic configured to:

in response to a processor core of the graphics processing unit requesting access to a region of a memory resource to output data as part of a second render, at a time the graphics processing unit has not completed processing a first render, enable that processor core to access that region of the resource if processing for the first render has been completed for that region.

Assignments (1)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →
Priority Claims (1)
GB 1907765 · May 31, 2019 · national
Continuity (3)
Continuation 17578774 · Jan 19, 2022
Continuation 16888763 · May 31, 2020
Related Publication 20240169642A1 · May 23, 2024
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