Trailing or leading digit anticipator
Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.
1. A leading zero anticipator configured to estimate a number of leading zeros in a result of an arithmetic operation performed on two or more fixed point numbers, the leading zero anticipator comprising:
an input encoding circuit configured to generate an encoded input string from the two or more fixed point numbers;
a surrogate string generation circuit configured to generate a surrogate string whose leading one is an estimate of a leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string; and
an output configured to provide the estimate of the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.
2. The leading zero anticipator of claim 1 , wherein a window of the encoded input string comprises a predetermined number of consecutive positions of the encoded input string.
3. The leading zero anticipator of claim 2 , wherein the predetermined number is greater than or equal to three.
4. The leading zero anticipator of claim 2 , wherein the surrogate string generation circuit is configured to generate a selected bit of the surrogate string based on a corresponding window of the encoded input string, the corresponding window comprising the predetermined number of consecutive positions of the encoded input string starting with and including a corresponding bit position of the encoded input string.
5. The leading zero anticipator of claim 1 , wherein the input encoding circuit is configured to set a selected position of the encoded input string to one of a z, p or g based on how many of the corresponding bits of the fixed point numbers are the predetermined value.
6. The leading zero anticipator of claim 5 , wherein there are two fixed point numbers and the input encoding circuit is configured to: set the selected position of the encoded input string to a z when both of the corresponding bits of the fixed point numbers are a first value; set the selected position of the encoded input string to a p when only one of the corresponding bits of the fixed point numbers is a second value; and set the selected position of the encoded input string to a g when both of the corresponding bits of the fixed point numbers are the second value.
7. The leading zero anticipator of claim 5 , wherein a window of the encoded input string comprises three consecutive positions of the encoded input string and the surrogate string generation circuit is configured to set a selected bit of the surrogate string to the predetermined value when the corresponding window of the encoded input string comprises ggz, gpg, gpp, gpz, gzg, pgg, pzz, zgz, zpg, zpp, zpz or zzg and the surrogate string generation circuit is configured to set the selected bit of the surrogate string to a different predetermined value when the corresponding window of the encoded input string comprises ggg, ggp, gzp, gzz, pgp, pgz, ppg, ppp, ppz, pzg, pzp, zgg, zgp, zzp, or zzz.
8. The leading zero anticipator of claim 5 , wherein the surrogate string generation circuit is configured to set a selected bit of the surrogate string, e_y, according to the following formula:
e _ y i =( ∧( p i−1 ∨( g i−1 ∧z i−2 )∨( z i−1 ∧g i−2 )))∨( p i ∧(( z i−1 ∧z i−2 )∨( g i−1 ∧g i−2 ))).
9. The leading zero anticipator of claim 5 , wherein the surrogate string generation circuit is configured to set a selected bit of a negated surrogate string, e_y , according to the following formula:
e _ y i =( p i ∧(( z i−1 ∧ g i−2 )∨( g i−1 ∧ z i−2 )))∨( p i ∧(( z i−1 ∧ g i−2 )∨( g i−1 ∧ z i−2 ))).
10. A method of estimating a number of leading zeros in a result of an arithmetic operation performed on two or more fixed point numbers, the method comprising:
generating, using an input-encoding circuit, an encoded input string from the two or more fixed point numbers;
generating, using a surrogate string generation circuit, a surrogate string whose leading one is an estimate of a leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string; and
outputting an estimate of the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.
11. The method of claim 10 , wherein a window of the encoded input string comprises a predetermined number of consecutive positions of the encoded input string and the predetermined number is greater than or equal to three.
12. The method of claim 11 , wherein generating the surrogate string comprises setting a selected bit of the surrogate string based on a corresponding window of the encoded input string, the corresponding window comprising the predetermined number of consecutive positions of the encoded input string starting with and including a corresponding bit position of the encoded input string.
13. The method of claim 10 , wherein generating the encoded input string comprises setting a selected position of the encoded input string to one of z, p or g based on how many of the corresponding bits of the fixed point numbers are the predetermined value.
14. The method of claim 13 , wherein there are two fixed point numbers and generating the encoded input string comprises: setting the selected position of the encoded input string to a z when both of the corresponding bits of the fixed point numbers are a first value; setting the selected position of the encoded input string to a p when only one of the corresponding bits of the fixed point numbers is a second value; and
setting the selected position of the encoded input string to a g when both of the corresponding bits of the fixed point numbers are the second value.
15. The method of claim 13 , wherein a window of the encoded input string comprises three consecutive positions of the encoded input string and generating the surrogate string comprises setting a selected bit of the surrogate string to the predetermined value when the corresponding window of the encoded input string comprises ggz, gpg, gpp, gpz, gzg, pgg, pzz, zgz, zpg, zpp, zpz or zzg and setting the selected bit of the surrogate string to a different predetermined value when the corresponding window of the encoded input string comprises ggg, ggp, gzp, gzz, pgp, pgz, ppg, ppp, ppz, pzg, pzp, zgg, zgp, zzp, or zzz.
16. The method of claim 13 , wherein generating the surrogate string comprises setting a selected bit of the surrogate string, e_y, according to the following formula:
e _ y i =( ∧( p i−1 ∨( p i−1 ∧z i−2 )∨( z i−1 ∧g i−2 )))∨
( p i ∧(( z i−1 ∧z i−2 )∨( g i−1 ∧g i−2 ))).
17. The method of claim 13 , wherein generating the surrogate string comprises setting a selected bit of a negated surrogate string, e_y , according to the following formula:
e _ y i =( p i ∧(( z i−1 ∧ g i−2 )∨( g i−1 ∧ z i−2 )))∨( p i ∧(( z i−1 ∧ g i−2 )∨( g i−1 ∧ z i−2 ))).
18. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the leading zero anticipator configured to estimate a number of leading zeros in a result of an arithmetic operation performed on two or more fixed point numbers, the leading zero anticipator comprising:
an input encoding circuit configured to generate an encoded input string from the two or more fixed point numbers;
a surrogate string generation circuit configured to:
generate a surrogate string whose leading one is an estimate of a leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string; and
an output configured to provide the estimate of the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.