IP Library Granted Patent US 11,423,285
Granted Patent B2
US 11,423,285 · App. 17/401,219 · Granted Aug 23, 2022

Buffer addressing for a convolutional neural network

Inventors: Daniel Barnard (Berkhamsted, GB); Clifford Gibson (St. Albans, GB); Colin McQuillan (Watford, GB)
Assignee: Imagination Technologies Limited
G06N3/04G06F12/0207G06F12/0607G06F12/0653G06N3/0454G06N3/063G06F2212/1016G06F2212/251
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Quick Facts
Patent No.
US 11,423,285
App. No.
17/401,219
Granted
Aug 23, 2022
Kind
B2
Abstract

Input data for a layer of a convolutional neural network (CNN) is provided by receiving input data values to be processed in a layer of the CNN. Addresses in banked memory of a buffer are determined in which the received data values are to be stored based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer. The received input data values are stored at the determined addresses in the buffer for retrieval for processing in the layer.

Claims (377)

1. A method of storing input data for a layer of a convolutional neural network, CNN, in a buffer comprising N B banks for processing, each bank comprising a plurality of words, the method comprising:

receiving input data comprising input data values to be processed in a layer of the CNN, the input data comprising P planes each with X columns and Y rows;

identifying a value, WordsPerLine, that indicates a number of words of each bank that will be required to store a row of the input data;

determining an address in the buffer in which each of the input data values are to be stored based on the WordsPerLine and a filter width m or a filter height N of a filter to be applied to the input data; and

storing the received input data values at the determined addresses in the buffer for retrieval for processing in the layer.

2. The method of claim 1 , wherein the WordsPerLine is equal to:

floor

(

(

P

*

X

+

N

B

-

1

N

B

)

)

*

N

B

3. The method of claim 1 , wherein the WordsPerLine is explicitly provided.

4. The method of claim 1 , wherein each input data value has a position in the input data defined by x, y and p co-ordinates reflecting a column, row and plane of the input data value respectively and an address in the buffer in which an input data value is to be stored is further based on the co-ordinates of that input data value.

5. The method of claim 4 , wherein each address in the buffer is defined by a first value, BANKSEL, indicating a bank of the buffer, and a second value, MEMADDR, indicating a memory location within the bank, and the MEMADDR of the address in the buffer in which an input data value is to be stored is determined by the following equation:

floor

(

(

x

*

P

+

p

+

y

*

WordsPerLine

N

B

)

)

%

MEMSIZE

wherein MEMSIZE is a number of addresses in each bank.

6. The method of claim 5 , wherein the BANKSEL of the address in the buffer in which an input data value is stored is determined by the following equation:

( x*P+p+y*m*P )% N B .

7. The method of claim 5 , wherein the BANKSEL of the address in the buffer in which an input data value is stored is determined by the following equation:

(

(

y

*

m

*

P

+

x

*

P

+

p

)

%

N

B

)

XOR

Reverse

(

(

x

NSB

)

%

NPU

)

wherein NPU is a largest power of two dividing P up to a maximum of N B ,

NSB

=

N

B

NPU

and Reverse(x) is a result of reversing all Log 2 (NPU) binary digits of x.

8. The method of claim 4 , wherein each address in the buffer is defined by a first value, BANKSEL, indicating a bank of the buffer, and a second value, MEMADDR, indicating a memory location within the bank, and the MEMADDR of the address in the buffer in which an input data value is to be stored is determined by the following equation:

(

MEMADDR

unwr

(

x

,

y

-

y

0

t

,

p

)

*

t

+

(

y

-

y

0

)

%

t

)

%

MEMSIZE

wherein

MEMADDR

unwr

(

x

,

y

,

p

)

=

x

*

P

+

p

+

y

*

WordsPerLine

N

B

,

MEMSIZE is a number of addresses in each bank, t is a vertical stride of the filter, and y 0 is a vertical position of a first row of the filter.

9. The method of claim 8 , wherein the BANKSEL of the address in the buffer in which an input data value is stored is determined by the following equation:

( x*P+p+y*m*P )% N B .

10. The method of claim 9 , wherein the method further comprises reading the input data values from the buffer in a plane, column, row order and passing the read input data values to convolution engines for processing.

11. The method of claim 8 , wherein the BANKSEL of the address in the buffer in which an input data value is stored is determined by the following equation:

(

(

y

*

m

*

P

+

x

*

P

+

p

)

%

N

B

)

XOR

Reverse

(

(

x

NSB

)

%

NPU

)

wherein NPU is a largest power of two dividing P up to a maximum of N B ,

NSB

=

N

B

NPU

and Reverse(x) is a result of reversing all Log 2 (NPU) binary digits of x.

12. The method of claim 11 , wherein the method further comprises reading the input data values from the buffer in a plane, column, row order and passing the read input data values to convolution engines for processing.

13. The method of claim 5 , wherein the BANKSEL of the address in the buffer in which an input data value is stored is determined by the following equation:

Hash( x +Hash(0 ,p;P ), y;N )% N B ,

wherein if N 2 ≤N B then

N

=

inverse

of

(

N

N

2

)

modulo

(

N

B

N

2

)

,

and

hash

(

x

,

y

;

N

)

=

(

x

+

N

*

(

y

N

2

)

)

%

(

N

B

N

2

)

+

(

(

x

N

2

+

y

)

%

N

2

)

*

(

N

B

N

2

)

otherwise hash(x,y;N)=y;

wherein if P 2 ≤N B then

P

=

inverse

of

(

P

P

2

)

modulo

(

N

B

P

2

)

,

and

hash

(

0

,

p

;

P

)

=

(

P

*

(

p

N

2

)

)

%

(

N

B

P

2

)

+

(

p

%

N

2

)

*

(

N

B

P

2

)

otherwise hash(0,p;P)=p;

wherein N 2 is a minimum of N B and a highest power of two dividing N;

wherein P 2 is a minimum of N B and a highest power of two dividing P.

14. The method of claim 13 , wherein the method further comprises reading the input data values from the buffer in a plane, row, column order and passing the read input data values to convolution engines for processing.

15. The method of claim 1 , further comprising:

receiving second input data comprising second input data values to be processed in a subsequent layer of the CNN, wherein the second input data is different to the input data;

determining an address in the buffer in which each of the second input data values are to be stored; and

storing the second input data values at the determined addresses in the buffer for retrieval for processing in the subsequent layer.

16. The method of claim 1 , further comprising receiving the input data from external memory.

17. Hardware logic for implementing a convolutional neural network, CNN, the hardware logic configured to:

receive input data comprising input data values to be processed in a layer of the CNN, the input data comprising P planes each with X columns and Y rows;

identify a value, WordsPerLine, that indicates a number of words of each bank that will be required to store a row of the input data;

determine an address in the buffer in which each of the input data values are to be stored based on the WordsPerLine and a filter width m or a filter height N of a filter to be applied to the input data; and

store the received input data values at the determined addresses in the buffer for retrieval for processing in the layer.

18. The hardware logic of claim 17 , wherein the hardware logic is embodied in hardware on an integrated circuit.

19. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the method as set forth in claim 1 .

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the hardware logic as set forth in claim 17 .

Assignments (1)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →