Floating point adder
An adder and a method for calculating 2 n +x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2 n +x for x<0 and 2 n−1 ≤|x|<2 n+1 ; a second path configured to calculate 2 n +x for |x|<2 n ; a third path configured to calculate 2 n +x for |x|≥2 n ; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.
1. An adder for calculating 2 n +x, where x is a variable input expressed in a floating point format and n is an integer, the adder comprising:
a small |x| path configured to calculate 2 n +x for |x|<2 n ;
a large |x| path configured to calculate 2 n +x for |x|≥2 n ; and
selection logic configured to cause the adder to output a result from one of the small |x| and large |x| paths in dependence on the values of x and n.
2. The adder according to claim 1 , wherein the selection logic is configured to select one of the small |x| and large |x| paths by:
if |x|<2 n , selecting the small |x| path, thereby causing the adder to output a result from the small |x| path; and
if the small |x| path is not selected, selecting the large |x| path, thereby causing the adder to output a result from the large |x| path.
3. The adder according to claim 1 , wherein the selection logic is configured to select one of the small |x| and large |x| paths by:
if |x|≥2 n , selecting the large |x| path, thereby causing the adder to output a result from the large |x| path; and
if the large |x| path is not selected, selecting the small |x| path, thereby causing the adder to output a result from the small |x| path.
4. The adder according to claim 1 , wherein the selection logic is configured to perform a comparison of |x| and 2 n to determine whether |x|<2 n or |x|≥2 n by comparing an exponent of x with n.
5. The adder according to claim 1 , wherein the adder is implemented in fixed-function circuitry, wherein the value of n is fixed in the fixed-function circuitry.
6. The adder according to claim 1 , further comprising mode switching logic configured to receive an indication of the value of n and to communicate the value of n to the selection logic and to the small |x| and large |x| paths.
7. The adder according to claim 1 , wherein the small |x| and large |x| paths do not comprise a renormaliser.
8. The adder according to claim 1 , wherein the small |x| path comprises a negation unit configured to, if x<0, negate an mantissa of x.
9. The adder according to claim 1 , wherein the small |x| path comprises a right shifter configured to align mantissa bits of x and 2 n .
10. The adder according to claim 1 , wherein the small |x| and large |x| paths each comprise a rounding unit configured to round the result of the respective path in accordance with a predefined rounding mode.
11. The adder according to claim 1 , wherein the selection logic comprises one or more multiplexers configured to receive a result from each of the paths, and to output the result from one of the paths in dependence on the values of x and n.
12. The adder according to claim 1 , wherein the paths are configured to commence calculation on receiving one or both of a mantissa and an exponent of x.
13. The adder according to claim 1 , wherein the selection logic is configured to select one of the small |x| and large |x| paths for use for a calculation and the selected path is used for that calculation, but the unselected path is not used for that calculation.
14. The adder according to claim 1 , wherein the large |x| path comprises integer addition logic configured to perform signed binary addition, and wherein the small |x| path does not comprise integer addition logic configured to perform signed binary addition.
15. The adder according to claim 1 , wherein the large |x| path is configured to add or subtract 2 n to or from a significand of x in dependence of whether x is positive or negative.
16. The adder according to claim 1 , wherein the large |x| path is configured to, if x<0, subtract 2 n from a mantissa of x and change a sign of the result.
17. The adder according to claim 1 , wherein the adder is configured to calculate x−2 n by changing a sign of x, calculating 2 n +x, and changing a sign of the result of calculating 2 n +x.
18. The adder according to claim 1 , wherein the adder is configured to calculate 2 n −x by changing a sign of x, and calculating 2 n +x.
19. A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture an adder for calculating 2 n +x, where x is a variable input expressed in a floating point format and n is an integer, the adder comprising:
a small |x| path configured to calculate 2 n +x for |x|<2 n ;
a large |x| path configured to calculate 2 n +x for |x|≥2 n ; and
selection logic configured to cause the adder to output a result from one of the small |x| and large |x| paths in dependence on values of x and n.
20. A method of calculating 2 n +x using an adder implemented in hardware, where x is a variable input expressed in a floating point format and n is an integer, wherein the adder comprises:
a small |x| path configured to calculate 2 n +x for |x|<2 n ; and
a large |x| path configured to calculate 2 n +x for |x|≥2 n ;
the method comprising:
receiving data representing the input, x;
providing at least some of the data representing x to one or more of the small |x| and large |x| paths for calculating 2 n +x;
selecting one of the small |x| and large |x| paths in dependence on values of x and n; and
outputting a result calculated by the selected path.