Multiple-input floating-point processing with mantissa bit extension

1. A method of processing a set of ‘k’ floating-point numbers to perform addition and/or subtraction, k≥3, using a hardware logic implementation, each floating-point number comprising a mantissa (m i ) and an exponent (e i ), wherein the method comprises:

receiving, by a format conversion circuit in the hardware logic implementation, the set of ‘k’ floating-point numbers in a first format, each floating-point number in the first format comprising a mantissa (m i ) with a bit-length of ‘b’ bits;

creating, by the format conversion circuit in the hardware logic implementation, a set of ‘k’ numbers (y i ) based on the mantissas of the ‘k’ floating-point numbers, the numbers (y i ) having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit-length ‘b’ of the mantissa (m i ), wherein the ‘n’ bits comprises a number of magnitude bits, wherein ‘n’ is b+┌log 2 (k)┐+┌log 2 (k−1)┐+x bits, where x is an integer, and x≥1 and x≤3, wherein adding the extra most-significant bits comprises adding at least ┌log 2 (k)┐ number of most-significant bits;

identifying, by a maximum exponent detection circuit in the hardware logic implementation, a maximum exponent (e max ) among the exponents e i ;

aligning, by an alignment circuit in the hardware logic implementation, the magnitude bits of the numbers (y i ) based on the maximum exponent (e max ); and

processing, by a processing circuit in the hardware logic implementation, the set of ‘k’ numbers (y i ) concurrently;

wherein processing of the set of ‘k’ numbers (y i ) by the processing circuit involves performing a computation that is required to perform a data processing function.

2. The method as claimed in claim 1 , wherein the set of ‘k’ floating-point numbers comprises:

unsigned floating-point numbers that implicitly includes a leading bit and x≥2; or

signed floating-point numbers that implicitly includes a leading bit and x=3.

3. The method as claimed in claim 1 , wherein the set of ‘k’ floating-point numbers comprises:

unsigned floating-point numbers that explicitly includes a leading bit and x≥1; or

signed floating-point numbers that explicitly includes a leading bit and x≥2.

4. The method as claimed in claim 1 , wherein x≤b.

5. The method as claimed in claim 1 , wherein adding the extra least-significant bits comprises adding at least ┌log 2 (k−1)┐+1 number of least-significant bits.

6. The method as claimed in claim 2 , wherein adding the extra most-significant bits comprises adding a leading bit if the received set of ‘k’ floating-point numbers in the first format implicitly include a leading bit, optionally wherein the method comprises forming the magnitude bits of the numbers (y i ) by prefixing the bits of the mantissa (m i ) of the floating-point number with the leading bit.

7. The method as claimed in claim 1 , wherein the method further comprises:

calculating an output value by processing ‘k’ numbers (y i );

renormalizing the output value; and

rounding the output value to represent the output value as a floating-point number.

8. The method as claimed in claim 1 , wherein aligning the magnitude bits of the numbers (y i ) to be based on the maximum exponent (e max ) comprises the steps of, for each floating-point number (i):

calculating the difference (e d ) between the maximum exponent (e max ) and exponent (e i ); and

shifting the magnitude bits of the corresponding number (y i ), to the LSB side, based on the calculated difference (e d ).

9. The method as claimed in claim 8 , wherein:

further to shifting the magnitude bits of the numbers (y i ), the method further comprises truncating the bits of the numbers (y i ) that are shifted outside the bit-length of the number; and/or

the method further comprises determining a two's complement of the magnitude bits of the numbers (y i ), based on a sign bit (s i ) of each corresponding floating-point number (i), if the set of ‘k’ floating-point numbers comprises signed floating-point numbers.

10. A hardware logic implementation for processing a set of k floating-point numbers to perform addition and/or subtraction, k≥3, each floating-point number comprising, a mantissa (m i ) and, an exponent (e i ), the hardware logic implementation comprising:

a format conversion circuit configured to:

receive the set of ‘k’ floating-point numbers in a first format, each floating-point number in the first format comprises the mantissa (m i ) with a bit-length of ‘b’ bits; and

convert the mantissa (m i ) of the set of ‘k’ floating-point numbers to a set of ‘k’ numbers (y i ), the numbers (y i ) having a bit-length of ‘n’ bits created by adding both extra most-significant bits and extra least-significant bits to the bit-length ‘b’ of the mantissa (m i ), where in the ‘n’ bits comprises a number of magnitude bits and wherein ‘n’ is b+┌log 2 (k)┐+┌log 2 (k−1)┐+x bits, where x is an integer, and x≥1 and x≤3, wherein adding the extra most-significant bits comprises adding at least ┌log 2 (k)┐ number of the most-significant bits;

a maximum exponent detection circuit configured to identify a maximum exponent (e max ) among the exponents e i ;

an alignment circuit configured to align the magnitude bits of the numbers (y i ) based on the maximum exponent (e max ); and

a processing circuit configured to process the set of ‘k’ numbers (y i ) concurrently to generate an output value;

wherein processing of the set of ‘k’ numbers (y i ) by the processing circuit involves performing a computation that is required to perform a data processing function.

11. The hardware logic implementation as claimed in claim 10 , wherein the format conversion circuit receives the set of ‘k’ floating-point numbers in a first format comprising:

unsigned floating-point numbers which explicitly includes a leading bit and x≥1; or

unsigned floating-point numbers which implicitly includes a leading bit and x≥2.

12. The hardware logic implementation as claimed in claim 10 , wherein the format conversion circuit receives the set of ‘k’ floating-point numbers in a first format comprising:

signed floating-point numbers which explicitly includes a leading bit and x≥2; or

signed floating-point numbers which implicitly includes a leading bit and x=3.

13. The hardware logic implementation as claimed in claim 10 , further comprises a renormalizing circuit configured to:

renormalize the output value; and

round the output value to represent the output value as a floating-point number.

14. The hardware logic implementation as claimed in claim 10 , wherein the format conversion circuit converts the mantissa (m i ) by adding a leading bit, if the received set of ‘k’ floating-point numbers in the first format implicitly include a leading bit.

15. The hardware logic implementation as claimed in claim 14 , wherein the format conversion circuit prefixes each mantissa (m i ) with the added leading bit while creating the numbers (y i ).

16. The hardware logic implementation as claimed in claim 10 , wherein the alignment circuit aligns the magnitude bits of the numbers (y i ) to be based on the maximum exponent (e max ), wherein the alignment circuit comprises:

a plurality of subtraction circuits, wherein each subtraction circuit is configured to calculate the difference (e d ) between the maximum exponent (e max ) and exponent (e i ) for each floating-point number (i); and

a plurality of shifter circuits, each shifter circuit configured to shift the magnitude bits of the corresponding number (y i ), to the LSB side, based on the calculated difference (e d ).

17. The hardware logic implementation as claimed in claim 16 , wherein the alignment circuit further truncates the bits of the numbers (y i ) that are shifted outside of the bit-length of the numbers (y i ).

18. The hardware logic implementation as claimed in claim 16 , wherein the alignment circuit further comprises a plurality of complementing circuits configured to determine two's complement of the magnitude bits of each number, based on a sign bit (s i ) of the corresponding floating-point number (i), if the set of ‘k’ floating-point numbers comprises signed floating-point numbers.

19. A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method of claim 1 to be performed when the computer readable code is run on at least one processor.