Assessing performance of a hardware design using formal evaluation logic

1. A hardware monitor arranged for use with a formal verification tool to assess performance of a hardware design for an integrated circuit to complete a set of tasks, the hardware monitor comprising:

monitoring and counting logic configured to:

monitor one or more control signals and/or data signals of an instantiation of the hardware design to identify start and completion of a symbolic task by the instantiation of the hardware design, the symbolic task representing the set of tasks; and

count a number of cycles between the start and the completion of the symbolic task; and

property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task.

2. The hardware monitor of claim 1 , wherein the one or more formal properties related to the counted number of cycles are configured such that evaluation of the one or more formal properties determines whether the instantiation of the hardware design completes the symbolic task within a predetermined number of cycles.

3. The hardware monitor of claim 1 , wherein the one or more formal properties related to the counted number of cycles are configured such that evaluation of the one or more formal properties identifies one or more performance metrics of the instantiation of the hardware design in completing the symbolic task.

4. The hardware monitor of claim 3 , wherein the one or more formal properties comprises one or more covered properties that state that the counted number of cycles is equal to a particular number of cycles.

5. The hardware monitor of claim 3 , wherein the one or more formal properties comprise a plurality of covered properties that each state that the counted number of cycles is equal to a different number of cycles.

6. The hardware monitor of claim 1 , wherein the one or more formal properties comprises one or more asserted properties that state that the counted number of cycles is less than a predetermined number.

7. The hardware monitor of claim 6 , wherein the one or more formal properties comprises an asserted property for each task of the set of tasks that states that if the symbolic task is that task the counted number of cycles is less than a predetermined number.

8. The hardware monitor of claim 1 , wherein the monitoring and counting logic comprises:

start event detection logic configured to monitor the one or more control signals and/or data signals of the instantiation of the hardware design to detect the start of the symbolic task, and in response to detecting the start of the symbolic task set a sampled in register;

end event detection logic configured to monitor the one or more control signals and/or data signals of the instantiation of the hardware design to detect the completion of the symbolic task, and in response to detecting the completion of the symbolic task when the sampled in register is set, set a sampled out register; and

counter update logic configured to increment a counter that represents the counted number of cycles when the sampled in register is set and the sampled out register is not set.

9. The hardware monitor of claim 1 , wherein the integrated circuit forms a processor.

10. The hardware monitor of claim 9 , wherein the monitoring and counting logic is configured to: detect the start of the symbolic task when a symbolic instruction has been fetched or decoded; and detect the completion of the symbolic task when the symbolic instruction has been executed.

11. The hardware monitor of claim 1 , wherein when the hardware design is processed in an integrated circuit manufacturing system, the hardware design configures the integrated circuit manufacturing system to manufacture the integrated circuit.