Communication interface between host system and state machine using event slot registers
A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.
1. A communications interface for interfacing between a host system and a state machine, the communications interface being arranged to control communication between different portions of a computing system, the communications interface comprising:
a plurality of event slots, each event slot comprising at least one register, the at least one register being for reading and writing by the host system, and the at least one register being addressable by the state machine;
wherein a first subset of event slots of the plurality of event slots and a second subset of event slots of the plurality of event slots are placed on respective access pages.
2. The communications interface as claimed in claim 1 , wherein the first subset of event slots and/or the second subset of event slots comprises a single event slot.
3. The communications interface as claimed in claim 1 , wherein the first subset of event slots and/or the second subset of event slots comprises more than one event slot.
4. The communications interface as claimed in claim 1 , wherein the first subset of event slots comprises a number, n 1 , of event slots, where n 1 is a power of 2.
5. The communications interface as claimed in claim 1 , wherein at least one event slot of the plurality of event slots is addressed from the host system by a single address location permitting the host system to write data to the at least one register by writing to the single address location, and read data from the at least one register by reading from the single address location.
6. The communications interface as claimed in claim 1 , wherein at least one event slot of the plurality of event slots comprises a plurality of registers, including:
a write register for writing by the host system, and
a read register for reading by the host system.
7. The communications interface as claimed in claim 1 , wherein at least one of the plurality of event slots is arranged to communicate with the state machine by placing at least one event index on an event queue.
8. The communications interface as claimed in claim 1 , wherein at least one of the plurality of event slots comprises:
a mask register for setting mask values, and
a reference register for storing reference information.
9. The communications interface as claimed in claim 1 , wherein at least two of the plurality of event slots are associated with different address locations.
10. The communications interface as claimed in claim 1 , wherein a firmware image determines at least one of:
an operation of the communications interface, and
a behaviour of the communications interface.
11. The communications interface as claimed in claim 1 , wherein the communications interface is embodied in an events handler, the events handler further comprising a state machine configured to execute at least one function stored in a memory in dependence on data passed through the communications interface and/or the communications interface is embodied in at least a part of a memory of a processing system for processing events.
12. The communications interface as claimed in claim 1 , wherein different security schemes are employed in each portion, and/or wherein each portion of the computing system comprises a memory management page.
13. The communications interface of claim 1 , wherein the communications interface is embodied in hardware on an integrated circuit.
14. The communications interface as claimed in claim 4 , wherein the second subset of event slots comprises a number, n 2 , of event slots, where n 2 is a power of 2.
15. The communications interface as claimed in claim 6 , wherein the write register and the read register are individually addressable by the state machine.
16. The communications interface as claimed in claim 8 , wherein the reference register is arranged to comprise a plurality of fields, the plurality of fields comprising:
at least one activate field for controlling an activation of events,
at least one function pointer index field for holding at least one function pointer index,
an interrupt number field for holding an interrupt line number, and
an interrupt enable field for holding an interrupt enable bit.
17. The communications interface as claimed in claim 16 , wherein the at least one of the plurality of event slots is arranged to communicate with the state machine by placing at least one event index on an event queue and wherein the at least one activate field comprises:
an activate on write field for indicating that a write function pointer index should be passed to the event queue,
an activate on read field for indicating that a read function pointer index should be passed to the event queue, and
an activate on interrupt acknowledge field for indicating that an interrupt function pointer index should be passed to the event queue.
18. A method of using a communications interface for interfacing between a host system and a state machine, the communications interface being arranged to control communication between different portions of a computing system, the communications interface comprising a plurality of event slots, each event slot comprising at least one register, the at least one register being for reading and writing by the host system, and the at least one register being addressable by the state machine, the method comprising:
placing a first subset of event slots of the plurality of event slots and a second subset of event slots of the plurality of event slots on respective access pages.
19. A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a communications interface arranged to control communication between different portions of a computing system, the communications interface comprising:
a plurality of event slots, each event slot comprising at least one register, the at least one register being for reading and writing by the host system, and the at least one register being addressable by the state machine;
wherein a first subset of event slots of the plurality of event slots and a second subset of event slots of the plurality of event slots are placed on respective access pages.