Compacting results vectors between stages of graphics processing
View Patent ↗Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set of input data elements and produce results. These results can be that the data elements can be categorized into different subsets, where each subset requires different processing as a next step. The data elements of these different subsets can be coalesced so that they are contiguous in a results set. The results set can be used to schedule additional computation, and if there are empty locations of a scheduling vector (after accounting for the members of a given subset), then those empty locations can be filled with other data elements that require the same further processing as that subset.
1. A system for processing rays in 3-D rendering, comprising:
a plurality of ray processing units, each ray processing unit comprising logic for testing a ray for intersection with one or more shapes comprising one or more elements of an acceleration structure, or one or more elements of geometry, and a memory configured to store definition data for rays that can be tested for intersection by that ray processing unit; and
a memory hierarchy configured to store data defining elements of the acceleration structure and elements of the geometry, and wherein the memory hierarchy is configured to store definition data for rays scheduled for ray testing, the definition data for rays containing both ray origin and ray direction data, wherein
each of the ray processing units is configured to receive data from an interconnect and to process the received data to identify, within the respective memory of that ray processing unit, one or more rays to be tested for intersection with a shape, and to output an indication of a result of the testing for intersection of that shape with the one or more identified rays.
2. The system of claim 1 , further comprising logic external to the ray processing units that is configured to receive the results of intersection testing from the ray processing units and to maintain status of traversal for one or more identified rays within the 3D scene.
3. The system of claim 2 , wherein each ray processing unit comprises logic for maintaining a portion of ray traversal status that collectively define ray traversal status for all rays that are currently being traversed in the 3-D scene.
4. The system of claim 2 , wherein the external logic is further configured to maintain state indicating which of the rays have definition data stored on the memory of each ray processing unit.
5. The system of claim 3 , wherein each of the ray processing units is configured to have an opportunity to output data on the interconnect, based on the portion of the ray traversal status maintained by that ray processing unit, and wherein others of the plurality of ray processing units are configured to receive that outputted data.
6. The system of claim 1 , wherein the data received from the interconnect comprises indications of one or more shapes to be tested.
7. The system of claim 1 , wherein each of the ray processing units is configured to maintain one or more collections of rays, and to output indications of the collections to the interconnect.
8. The system of claim 1 , wherein each ray processing unit is configured to be responsive to indications of results of intersection testing outputted from another ray processing unit and transmitted through the interconnect.
9. The system of claim 1 , wherein the data received from the interconnect comprises ray identifiers for identifying rays within the memories of the ray processing units.
10. The system of claim 1 , wherein the memories of the ray processing units are caches.
11. The system of claim 1 , wherein each of the plurality of ray processing units is connected to one or more of the other ray processing units by queues of the interconnect in a ring architecture.
12. The system of claim 11 , wherein the queues are configured to allow data to be passed between ray processing units in one direction around the ring architecture.
13. The system of claim 11 , wherein the queues are configured to allow data to be passed between ray processing units in two directions around the ring architecture.
14. The system of claim 11 , wherein at least one of the ray processing units is configured to:
output a packet around the ring architecture, wherein the packet comprises indications of a collection of rays and an indication of a shape with which the rays of the collection are to be intersection tested; and
subsequently receive the packet, wherein the received packet is populated with results of testing the indicated shape for intersection with rays identified in the packet for which definition data is stored in the memories of the other ray processing units.
15. A method of processing rays using a plurality of ray processing units, each of the ray processing units being associated with a respective memory which stores definition data for rays that can be tested for intersection by that ray processing unit, the method comprising, at each of the ray processing units:
receiving data from an interconnect;
processing the received data to identify, within the respective associated memory of that ray processing unit, one or more rays to be tested for intersection with a shape, said shape comprising one or more elements of an acceleration structure, for one or more elements of geometry, wherein the memory is configured to store definition data for rays scheduled for ray testing, the definition data for rays containing both ray origin and ray direction data; and
outputting an indication of a result of the testing for intersection of that shape with the one or more identified rays.
16. The method of claim 15 , wherein each of the ray processing units maintains one or more collections of rays, and outputs indications of the collections to the interconnect.
17. The method of claim 15 , further comprising fetching data for the shape from a memory.
18. The method of claim 15 , wherein each of the plurality of ray processing units is connected to one or more of the other ray processing units by queues of the interconnect in a ring architecture.
19. The method of claim 18 , wherein at least one of the ray processing units:
outputs a packet around the ring architecture, wherein the packet comprises indications of a collection of rays and an indication of a shape with which the rays of the collection are to be intersection tested; and
subsequently receives the packet, wherein the received packet is populated with results of testing the indicated shape for intersection with rays identified in the packet for which definition data is stored in the memories of the other ray processing units.
20. A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when processed at a computer system for generating a manifestation of an integrated circuit, cause the computer system to generate a manifestation of a system for processing rays in a 3-D rendering, wherein the system comprises:
a plurality of ray processing units, each ray processing unit comprising logic for testing a ray for intersection with one or more shapes comprising one or more elements of an acceleration structure, or one or more elements of geometry, and a memory configured to store definition data for rays that can be tested for intersection by that ray processing unit; and
a memory hierarchy configured to store data defining elements of the acceleration structure and elements of the geometry, wherein the memory hierarchy is configured to store definition data for rays scheduled for ray testing, the definition data for rays containing both ray origin and ray direction data, wherein
each of the ray processing units is configured to receive data from an interconnect and to process the received data to identify, within the respective memory of that ray processing unit, one or more rays to be tested for intersection with a shape, and to output an indication of a result of the testing for intersection of that shape with the one or more identified rays.