HARDWARE EFFICIENT ROUNDING

1 . A computer-implemented method of rounding an unsigned normalised n-bit number to an m-bit number, the method comprising:

receiving the n-bit number in a binary format;

determining a correction value having a bit length of n bits, wherein determining the correction value comprises shifting the n-bit number by m bits;

determining a pre-truncation value having a bit length of n bits based on at least the n-bit number, the correction value, a value for the most significant bit (MSB) of the n-bit number, and a rounding value having a ‘1’ at the n−mth bit position and a ‘0’ at all other bits; and

obtaining the rounded m-bit number by truncating the n−m least significant bits (LSB) of the pre-truncation value.

2 . The computer-implemented method as claimed in claim 1 , wherein determining the pre-truncation value comprises performing one or more addition and/or subtraction operations on the n-bit number, the rounding value, the correction value and the value for the MSB of the n-bit number.

3 . The computer-implemented method as claimed in claim 1 , wherein the rounding value is determined by shifting a value of ‘1’ to the left by n−m−1 bits thereby positioning a 1 bit at the n−mth bit position.

4 . The computer-implemented method as claimed in claim 1 , wherein the value of MSB of the n-bit number is identified by shifting the number to the right by n−1 bits.

5 . The computer-implemented method as claimed in claim 1 , wherein determining a pre-truncation value comprises:

subtracting the correction value from the n-bit number;

subtracting an inverted version of the MSB value from the rounding value; and

adding the output from the two subtractions to generate the pre-truncation value.

6 . The computer-implemented method as claimed in claim 5 , wherein the inverted version of the MSB value is obtained by performing a NOT operation on the LSB of the MSB value.

7 . The computer-implemented method as claimed in claim 1 , wherein determining a pre-truncation value comprises:

inverting the correction value; and

adding the inverted correction value, rounding value and the value of MSB of the n-bit number to the n-bit number to generate the pre-truncation value.

8 . The computer-implemented method as claimed in claim 7 , wherein inverting the correction value comprises performing a NOT operation on the bits of the correction value.

9 . A binary logic circuit for rounding an unsigned normalised n-bit number to an m-bit number, the binary logic circuit comprising:

an input configured to receive the n-bit number;

correction value logic configured to generate a correction value having a bit length of n bits, the logic comprising a shifter for shifting the n-bit number by m bits;

MSB value logic configured to determine the MSB value of the n-bit number;

pre-truncation value logic configured to determine a pre-truncation value having a bit length of n bits based on at least the n-bit number, the correction value, the MSB value of the received number, and a rounding value having a ‘1’ at the n−mth bit position and a ‘0’ at all other bits;

truncation logic configured to truncate the pre-truncation value by discarding the n−m LSB bits to obtain a rounded m-bit number; and

an output configured to output the rounded m-bit number.

10 . The binary logic circuit as claimed in claim 9 , wherein the pre-truncation value logic determines a pre-truncation value by performing one or more addition and/or subtraction operations on the n-bit number, the rounding value, the correction value and the value for the MSB of the n-bit number.

11 . The binary logic circuit as claimed in claim 9 , further comprising rounding value logic configured to determine the rounding value by shifting value of ‘1’ to the left by n−m−1 bits thereby positioning a ‘1’ bit at the n−m th bit position.

12 . The binary logic circuit as claimed in claim 9 , wherein the MSB value logic identifies the value of MSB of the number by shifting the number to the right by n−1 bits.

13 . The binary logic circuit as claimed in claim 9 , wherein the pre-truncation value logic comprises:

a first subtractor for subtracting the correction value from the n-bit number;

a second subtractor for subtracting an inverted version of the MSB value from the rounding value; and

an adder for adding the output from the first subtractor and the second subtractor to generate the pre-truncation value.

14 . The binary logic circuit as claimed in claim 13 , wherein the inverted version of the MSB value is obtained by performing a NOT operation on the LSB of the MSB value.

15 . The binary logic circuit as claimed in claim 9 , wherein the pre-truncation value logic comprises a plurality of adders configured to add an inverted version of the correction value, the rounding value and the MSB value to the received n-bit number to generate the pre-truncation value.

16 . The binary logic circuit as claimed in claim 15 , wherein the correction value logic further comprises NOT logic configured to generate the inverted correction value.

17 . An image compression circuit comprising the binary logic circuit for rounding an n-bit number to an m-bit number as set forth in claim 9 .

18 . The binary logic circuit of claim 9 , wherein the binary logic circuit is embodied in hardware on an integrated circuit.

19 . A method of manufacturing a binary logic circuit as set forth in claim 9 , comprising inputting a computer-readable dataset description of said binary logic circuit into an integrated circuit manufacturing system, causing said integrated circuit manufacturing system to manufacture said binary logic circuit.

20 . A non-transitory computer readable storage medium having encoded thereon computer readable code configured to cause the computer-implemented method as set forth in claim 1 to be performed when the code is run.