Small multiplier after initial approximation for operations with increasing precision
In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.
1. An apparatus for performing an iterative arithmetic operation on an input value to obtain an output value that is used to execute an instruction requesting an arithmetic operation on an operand by said input value, comprising:
initial approximation circuitry configured to provide, based on at least a portion of said input value, an initial approximation of said output value;
limited precision multiplier circuitry configured to obtain a first multiplication result of a first iteration;
full-precision multiplier circuitry configured to obtain a second multiplication result of the first iteration; and
an output configured to output said output value.
2. The apparatus of claim 1 , wherein the initial approximation of the output value has a second number of bits of precision that is less than a first number of bits of precision to which said output value is to be produced.
3. The apparatus of claim 1 , wherein the second multiplication result has a number of bits of precision that is the same as or greater than a first number of bits of precision to which said output value is to be produced.
4. The apparatus of claim 1 , wherein the full-precision multiplier circuitry requires a first number of clock cycles to finish its multiplication, and a combined number of clock cycles required by the initial approximation circuitry to provide the initial approximation and the limited precision multiplier circuitry to complete a multiplication is equal to or less than the first number of clock cycles.
5. The apparatus of claim 1 , wherein a mantissa for the output value is obtained by conducting an iterative refinement of the initial approximation, wherein a first multiplication in the iterative refinement is conducted by the limited precision multiplier circuitry and subsequent multiplications in the iterative refinement are conducted by the full precision multiplier circuitry.
6. The apparatus of claim 1 , wherein the initial approximation circuitry comprises a LookUp Table (LUT) configured to receive at least a portion of bits of the input value and to output a set of bits from which the initial approximation can be constructed.
7. The apparatus of claim 1 , wherein the full-precision multiplier circuitry is configured to perform a double-precision multiplication between two mantissas.
8. The apparatus of claim 1 , wherein the apparatus is configured to provide a value for a division of a dividend a by a divisor b, and the initial approximation circuitry is configured to produce the initial approximation as an initial approximation of a reciprocal of the divisor b.
9. The apparatus of claim 1 , wherein the apparatus is configured to provide a value for a square root of a value b and the initial approximation circuitry is configured to produce the initial approximation as an initial approximation of a reciprocal of the square root of b.
10. The apparatus of claim 1 , wherein the full-precision multiplier circuitry is further configured to feed the second multiplication result back as an input to the full-precision multiplier circuitry to iteratively refine said output value.
11. The apparatus of claim 10 , wherein the initial approximation of the output value has a second number of bits of precision that is less than a first number of bits of precision to which said output value is to be produced.
12. The apparatus of claim 10 , wherein the second multiplication result has a number of bits of precision that is the same as or greater than a first number of bits of precision to which said output value is to be produced.
13. The apparatus of claim 10 , wherein the full-precision multiplier circuitry requires a first number of clock cycles to finish its multiplication, and a combined number of clock cycles required by the initial approximation circuitry to provide the initial approximation and the limited precision multiplier circuitry to complete a multiplication is equal to or less than the first number of clock cycles.
14. The apparatus of claim 10 , wherein a mantissa for the output value is obtained by conducting an iterative refinement of the initial approximation, wherein a first multiplication in the iterative refinement is conducted by the limited precision multiplier circuitry and subsequent multiplications in the iterative refinement are conducted by the full precision multiplier circuitry.
15. The apparatus of claim 10 , wherein the initial approximation circuitry comprises a LookUp Table (LUT) configured to receive at least a portion of bits of the input value and to output a set of bits from which the initial approximation can be constructed.
16. The apparatus of claim 10 , wherein the full-precision multiplier circuitry is configured to perform a double-precision multiplication between two mantissas.
17. The apparatus of claim 10 , wherein the apparatus is configured to provide a value for a division of a dividend a by a divisor b, and the initial approximation circuitry is configured to produce the initial approximation as an initial approximation of a reciprocal of the divisor b.
18. The apparatus of claim 10 , wherein the apparatus is configured to provide a value for a square root of a value b and the initial approximation circuitry is configured to produce the initial approximation as an initial approximation of a reciprocal of the square root of b.