Guaranteed data compression using intermediate compressed data
Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
1. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n>m, the method comprising:
determining, in a truncation hardware unit, an intermediate m-bit number;
adding, in an increment/decrement hardware unit, an adjustment value to the intermediate m-bit number to generate the output m-bit number.
2. The method according to claim 1 , wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.
3. A method of frame buffer compression, comprising the steps of claim 1 .
4. The method of claim 3 , wherein the method of frame buffer compression further comprises:
storing one or more bits of pixel data in a frame buffer; and
outputting the stored one or more bits of pixel data to a display.
5. Hardware logic configured to perform the method of claim 1 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.
6. A data compression unit comprising the hardware logic according to claim 5 .
7. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 1 .
8. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n<m, the method comprising:
determining, in a replication hardware unit, an intermediate m-bit number;
adding, in an increment/decrement hardware unit, an adjustment value to the intermediate m-bit number to generate the output m-bit number.
9. The method according to claim 8 , wherein if m>2n, determining an intermediate m-bit number comprises:
appending (k−1) repetitions of the input n-bit number to the input n-bit number followed by r most significant bits of the input n-bit number, where k=└(m/n)┘ and r=m mod n.
10. The method according to claim 8 , wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.
11. Hardware logic configured to perform the method of claim 8 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.
12. A data compression unit comprising the hardware logic according to claim 11 .
13. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 8 .
14. Hardware logic arranged to map an input n-bit number to an output m-bit number, where n and m are integers and n>m, the hardware logic comprising:
a truncation hardware unit arranged to determine an intermediate m-bit number;
an increment/decrement hardware unit arranged to add an adjustment value to the intermediate m-bit number to generate the output m-bit number.
15. A data compression unit comprising the hardware logic according to claim 14 .
16. A method of manufacturing, using an integrated circuit manufacturing system, hardware logic as set forth in claim 14 .
17. An integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 14 .
18. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 14 .
19. An integrated circuit manufacturing system configured to manufacture hardware logic as set forth in claim 14 .
20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that describes hardware logic as set forth in claim 14 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the hardware logic; and
an integrated circuit generation system configured to manufacture the hardware logic according to the circuit layout description.