Conversion of a normalized n-bit value into a normalized m-bit value

1. A method of processing data in a processor by converting in computing logic a normalized n-bit data value which represents one of 2 n evenly spaced values within a particular range into a normalized m-bit value which represents one of 2 m evenly spaced values within the particular range in accordance with a predetermined rounding mode, the method comprising:

receiving the normalized n-bit value at an initial module of the computing logic;

determining, by the initial module, an initial m-bit value, wherein the bits of said initial m-bit value are determined to be equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the received normalized n-bit value;

based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode, selecting at a selection module of the computing logic an output state indicating a predefined manner of determining the normalized m-bit value from the initial m-bit value;

in accordance with the selected output state, determining, at an output module of the computing logic, from the normalized n-bit value the normalized m-bit value to be equal to one of a plurality of candidate m-bit values, the plurality of candidate m-bit values consisting of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one; and

outputting, from the output module, the determined normalized m-bit value converted from the normalized n-bit data value, whereby the data represented by the normalized n-bit data value can be processed in a processor using the normalized m-bit value.

2. The method of claim 1 wherein the bits of said initial m-bit value are determined to be equal to the m most significant bits of a concatenation of

⌈

m

n

⌉

copies of the received normalized n-bit value.

3. The method of claim 1 wherein said selecting an output state comprises determining a value of a subtraction of a first arrangement of the bits of the normalized n-bit value from a second arrangement of the bits of the normalized n-bit value.

4. The method of claim 3 wherein the first arrangement is equal to the n bits of the normalized n-bit value having r most significant bits and n−r least significant bits, and wherein the second arrangement is equal to n bits comprising the r most significant bits of the normalized n-bit value appended to the n−r least significant bits of the normalized n-bit value, where r=m mod n.

5. The method of claim 4 wherein said determining a value of the subtraction comprises determining the sign of the result of the subtraction.

6. The method of claim 5 wherein the sign of the result of the subtraction is determined using an (n−k)-bit subtractor, where k is the greatest common divisor of n and m.

7. The method of claim 4 wherein the predetermined rounding mode is a rounding mode in which non-integer values are rounded to the nearest integer, and wherein said determining a value of the subtraction comprises determining whether the result of the subtraction divided by 2 n lies within a first range of −1 to −½, within a second range of −½ to +½, or within a third range of +½ to 1.

8. The method of claim 7 wherein in accordance with the predetermined rounding mode, the plurality of candidate m-bit values consists of the initial m-bit value, the initial m-bit value incremented by one and the initial m-bit value decremented by one.

9. The method of claim 7 wherein the value of the subtraction is determined using an (n−k+1)-bit subtractor, where k is the greatest common divisor of n and m.

10. The method of claim 1 wherein the predetermined rounding mode is a rounding mode in which non-integer values are rounded down to the next integer.

11. The method of claim 10 wherein in accordance with the predetermined rounding mode, the plurality of candidate m-bit values consists of the initial m-bit value and the initial m-bit value decremented by one.

12. The method of claim 10 wherein:

if r=1 said selecting an output state comprises determining the value of a function f 1 represented by a logic equation given by x n-1 ( x 0 + x 1 + x 2 + . . . + x n-3 + x n-2 ) and selecting an output state in dependence on the value of f 1 ; and

if r=n−1 said selecting an output state comprises determining the value of a function f 2 represented by a logic equation given by x 0 (x 1 +x 2 +x 3 + . . . +x n-2 +x n-1 ) and selecting an output state in dependence on the value of f 2 ,

where x 0 to x n-1 are the n bits of the normalized n-bit value, and where r=m mod n.

13. The method of claim 1 wherein the predetermined rounding mode is a rounding mode in which non-integer values are rounded up to the next integer.

14. The method of claim 13 wherein in accordance with the predetermined rounding mode, the plurality of candidate m-bit values consists of the initial m-bit value and the initial m-bit value incremented by one.

15. The method of claim 13 wherein if m≡±1 mod n, then the normalized m-bit value is determined to be equal to the initial m-bit value.

16. A processing unit comprising computing logic configured to convert a normalized n-bit data value which represents one of 2 n evenly spaced values within a particular range into a normalized m-bit value which represents one of 2 m evenly spaced values within the particular range in accordance with a predetermined rounding mode, the logic comprising:

an initial module configured to:

receive the normalized n-bit data value, and

determine an initial m-bit value such that the bits of said initial m-bit value are equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the received normalized n-bit value;

a selection module configured to select an output state based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode, said output state indicating how the normalized m-bit value is to be determined from the initial m-bit value; and

an output module configured to:

determine the normalized m-bit value from the normalized n-bit data value, in accordance with the selected output state, to be equal to one of a plurality of candidate m-bit values, the plurality of candidate m-bit values consisting of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one; and

output the determined normalized m-bit value converted from the normalized n-bit value, whereby the data represented by the normalized n-bit data value can be processed in a processor using the normalized m-bit value.

17. The processing unit of claim 16 wherein the selection module comprises a subtractor, and wherein the selection module is configured to select said output state by using the subtractor to determine a sign of the result of a subtraction of the n bits of the normalized n-bit value having r most significant bits and n−r least significant bits from n bits comprising the r most significant bits of the normalized n-bit value appended to the n−r least significant bits of the normalized n-bit value, where r=m mod n.

18. The processing unit of claim 17 wherein the subtractor is an (n−k)-bit subtractor configured to determine the sign of the result of the subtraction, where k is the greatest common divisor of n and m.

19. The processing unit of claim 16 wherein the output module comprises a multiplexer configured to determine the normalized m-bit value, the multiplexer having:

at least two data inputs configured to receive respective candidate m-bit values of the plurality of candidate m-bit values; and

a control input configured to receive an indication of the output state from the selection module, for use in selecting one of the candidate m-bit values to provide as the output from the output module, thereby determining the normalized m-bit value.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed, causes an integrated circuit manufacturing system to generate a manifestation of computing logic configured to convert a normalized n-bit data value which represents one of 2 n evenly spaced values within a particular range into a normalized m-bit value which represents one of 2 m evenly spaced values within the particular range in accordance with a predetermined rounding mode by:

receiving at an initial module of the logic the normalized n-bit value;

determining at the initial module an initial m-bit value, wherein the bits of said initial m-bit value are determined to be equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the received normalized n-bit value;

based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode, selecting at a selection module an output state indicating how the normalized m-bit value is to be determined from the initial m-bit value;

in accordance with the selected output state, determining at an output module from the normalized n-bit data value the normalized m-bit value to be equal to one of a plurality of candidate m-bit values, the plurality of candidate m-bit values consisting of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one; and

outputting, from the output module, the determined normalized m-bit value converted from the normalized n-bit value, whereby the data represented by the normalized n-bit data value can be processed in a processor using the normalized m-bit value.