Clock frequency adjustment for semi-conductor devices
A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.
1. A method of providing a clock signal to a processing module comprising:
modifying a clock signal at a clock deletion circuit, wherein the clock signal has a pattern of pulses, and wherein modifying the clock signal comprises removing one or more pulses from the pattern of pulses in dependence on a control signal, wherein the clock deletion circuit comprises: (i) a clock deletion control unit configured to receive the clock signal and the control signal, and to generate a series of pulses, and (ii) a clock gating cell configured to receive the clock signal and the generated series of pulses, and to generate the modified clock signal; and
providing the modified clock signal to the processing module;
wherein the control signal is dynamically adjusted by the processing module.
2. A method as claimed in claim 1 , wherein the modified clock signal has a different duty cycle to the clock signal.
3. A method as claimed in claim 1 , wherein the modified clock signal has a different frequency to the clock signal.
4. A method as claimed in claim 1 , wherein the frequency of the clock signal is variable and dependent on a process running on the processing module.
5. A method as claimed in claim 1 , wherein the control signal contains data relating to the required clock frequency which is to be applied to the processing module.
6. A method as claimed in claim 1 , further comprising determining a performance metric for the processing module, the control signal being generated in dependence on the performance metric.
7. A method as claimed in claim 6 , wherein the performance metric is generated using a state of a buffer of the processing module.
8. A method as claimed in claim 1 , wherein the processing module is comprised within a System On Chip (SOC).
9. A method as claimed in claim 8 , wherein the control signal is generated in dependence on a flow of data in the System.
10. A circuit for providing a clock signal to a processing module comprising:
a clock deletion circuit for the processing module, wherein the clock deletion circuit is configured to modify a clock signal, wherein the clock signal has a pattern of pulses, by removing one or more pulses from the pattern of pulses in dependence on a control signal, wherein the clock deletion circuit comprises: (i) a clock deletion control unit configured to receive the clock signal and the control signal, and to generate a series of pulses, and (ii) a clock gating cell configured to receive the clock signal and the generated series of pulses, and to generate the modified clock signal;
wherein the control signal is dynamically adjusted by the processing module.
11. A circuit as claimed in claim 10 , wherein the modified clock signal has a different duty cycle to the clock signal.
12. A circuit as claimed in claim 10 , wherein the modified clock signal has a different frequency to the clock signal.
13. A circuit as claimed in claim 10 , wherein the frequency of the clock signal is variable and dependent on a process running on the processing module.
14. A circuit as claimed in claim 10 , wherein the control signal contains data relating to the required clock frequency which is to be applied to the processing module.
15. A circuit as claimed in claim 10 , wherein the processing module is comprised within a System On Chip (SOC).
16. A circuit as claimed in claim 15 , wherein the control signal is generated in dependence on a flow of data in the System.
17. A System On Chip comprising:
a clock signal having a pattern of pulses;
a processing module;
a clock control unit configured to generate a control signal;
a clock deletion circuit configured to modify the clock signal by removing one or more pulses from the pattern of pulses in dependence on the control signal, wherein the clock deletion circuit comprises: (i) a clock deletion control unit configured to receive the clock signal and the control signal, and to generate a series of pulses, and (ii) a clock gating cell configured to receive the clock signal and the generated series of pulses, and to generate the modified clock signal;
wherein the control signal is dynamically adjusted by the processing module.
18. A System On Chip as claimed in claim 17 , wherein the modified clock signal has a different duty cycle to the clock signal.
19. A System on Chip as claimed in claim 17 , wherein the modified clock signal has a different frequency to the clock signal.
20. A System On Chip as claimed in claim 17 , wherein the frequency of the clock signal is variable and dependent on a process running on the processing module.