IP Library Granted Patent US 12,633,043
Granted Patent B1
US 12,633,043 · App. 18/594,863 · Granted May 19, 2026

Coarse depth test in graphics processing systems

Inventors: Lorenzo Belli (Watford, GB); Robert Brigg (Watford, GB)
Assignee: Imagination Technologies Limited
G06T15/405G06F7/24G06F9/4881G06T1/60G06T7/50G06T15/20G06T15/40G06T17/10G06T2207/10028G06T2207/20021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,633,043
App. No.
18/594,863
Granted
May 19, 2026
Kind
B1
Abstract

Coarse depth testing is performed in a graphics processing system having a rendering space divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range as to whether all or a portion of a primitive is hidden in the tile. If at least a portion is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed. If so, the primitive or primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.

Claims (52)

1 . Coarse depth test hardware configured to perform coarse depth testing in a graphics processing system in which a rendering space is subdivided into a plurality of tiles, the coarse depth test hardware comprising:

front depth test logic configured to:

receive a set of one or more primitives or a set of one or more primitive fragments related to a tile of the plurality of tiles;

obtain a depth range for the tile, the depth range for the tile identifying a depth range based on primitives or primitive fragments previously processed for the tile; and

for at least one primitive of the set of one or more primitives or at least one primitive fragment of the set of one or more primitive fragments:

make a determination, based on the depth range for the tile, as to whether the primitive or primitive fragment is in front of the primitives or primitive fragments previously processed for the tile according to a depth compare mode, and

in response to making a determination that the primitive or primitive fragment is in front of the primitives or primitive fragments previously processed for the tile, identifying the primitive or primitive fragment as not requiring a read of a depth buffer to perform full resolution depth testing.

2 . The coarse depth test hardware of claim 1 , wherein the front depth test logic is further configured to:

maintain a record of each pixel sample in the tile for which a best depth value is available;

in response to making a determination that a primitive or a primitive fragment is not in front of the primitives or primitive fragments previously processed for the tile, make a determination as to whether the record indicates that the best depth value is available for each pixel sample in the tile associated with that primitive or primitive fragment;

in response to making a determination that the record indicates that the best depth value is available for each pixel sample in the tile associated with that primitive or primitive fragment, identify the primitive or primitive fragment as not requiring a read of the depth buffer to perform full resolution depth testing; and

in response to making a determination that a primitive or primitive fragment has better depth than the primitives or primitive fragments previously processed for the tile, update the record to indicate that the best depth value is available for each pixel sample in the tile associated with that primitive or primitive fragment.

3 . The coarse depth test hardware of claim 2 , wherein the front depth test logic is further configured to, in response to not identifying a primitive or a primitive fragment as not requiring a read of the depth buffer to perform full resolution depth testing, update the record to indicate that the best depth value is available for each pixel sample in the tile.

4 . The coarse depth test hardware of claim 2 , wherein the record is a pixel sample map comprising a bit for each pixel sample in the tile that indicates whether or not the best depth value is available for that pixel sample.

5 . The coarse depth test hardware of claim 1 , wherein the front depth test logic is further configured to:

maintain a record of each pixel sample in the tile for which a best depth value is available;

in response to making a determination that a primitive or a primitive fragment is in front of the primitives or primitive fragments previously processed for the tile:

determine whether the record indicates that the best depth value is available for each pixel sample in the tile associated with that primitive or that primitive fragment,

in response to making a determination that the record indicates that the best depth value is not available for any of the pixel samples in the tile associated with that primitive or that primitive fragment, identify the primitive or primitive fragment as not requiring a full resolution depth test, and

update the record to indicate that the best depth value is available for each pixel sample in the tile associated with that primitive or that primitive fragment; and

in response to not identifying a primitive or primitive fragment as not requiring a read of the depth buffer to perform full resolution depth testing, update the record to indicate that the best depth value is available for each pixel sample in the tile.

6 . The coarse depth test hardware of claim 5 , wherein the record is a pixel sample map comprising a bit for each pixel sample in the tile that indicates whether or not the best depth value is available for that pixel sample.

7 . The coarse depth test hardware of claim 1 , wherein the front depth test logic is further configured to:

maintain a record of each pixel sample in the tile for which a best depth value is available;

in response to making a determination that a primitive or a primitive fragment is in front of the primitives or primitive fragments previously processed for the tile:

make a determination as to whether the record indicates that the best depth value is available for each pixel sample in the tile associated with that primitive or that primitive fragment,

for each pixel sample in the tile associated with that primitive or that primitive fragment in which the best depth value is not available, identify a corresponding primitive fragment as not requiring a full resolution depth test, and

updating the record to indicate that the best depth value is available for each pixel sample in the tile associated with that primitive or that primitive fragment; and

in response to not identifying a primitive or a primitive fragment as not requiring a read of the depth buffer to perform full resolution depth testing, update the record to indicate that the best depth value is available for each pixel sample in the tile.

8 . The coarse depth test hardware of claim 1 , wherein the depth range for the tile is defined by a maximum depth value for the tile and a minimum depth value for the tile.

9 . The coarse depth test hardware of claim 8 , wherein the front depth test logic is configured to determine whether a primitive or a primitive fragment is in front of the primitives or primitive fragments previously processed for the tile by comparing one of the maximum depth value for the tile and the minimum depth value for the tile with one of a maximum depth value of the primitive or the primitive fragment in the tile and a minimum depth value of the primitive or primitive fragment in the tile.

10 . The coarse depth test hardware of claim 8 , wherein a less-than-depth compare mode is used and the front depth test logic is configured to make a determination as to whether a primitive or primitive fragment is in front of the primitives or primitive fragments previously processed for the tile by determining if a maximum depth value of that primitive or primitive fragment in the tile is less than the minimum depth value of the tile.

11 . The coarse depth test hardware of claim 1 , further comprising depth range update logic configured to:

record a best depth, based on the depth range for the tile, as a current best depth value;

when the front depth test logic has made a determination that a primitive or primitive fragment is in front of the primitives or primitive fragments previously processed for the tile, receive from the front depth test logic a depth value of that primitive or primitive fragment in the tile from the front depth test logic;

compare the received depth value to the current best depth value;

in response to determining that the received depth value is better than the current best depth value, update the current best depth value with the received depth value; and

in response to determining that the front depth test logic has processed each primitive in the set of one or more primitives or each primitive fragment in the set of one or more primitive fragments, update the depth range for the tile to reflect the current best depth value.

12 . The coarse depth test hardware of claim 1 , wherein the front depth test logic is configured to use the same depth range for the tile for all primitives in the set of one or more primitives or for all primitive fragments in the set of one or more primitive fragments.

13 . The coarse depth test hardware of claim 1 , wherein the front depth test logic is configured to receive the set of one or more primitive fragments.

14 . The coarse depth test hardware of claim 13 , wherein the set of one or more primitive fragments comprises primitive fragments generated from a set of one or more primitives determined not to be hidden by the primitives or primitives fragments previously processed for the tile.

15 . The coarse depth test hardware of claim 1 , further comprising a memory configured to store the depth range for the tile.

16 . A graphics processing system comprising the coarse depth test hardware as set forth in claim 1 .

17 . The graphics processing system of claim 16 , further comprising hidden surface removal logic configured to perform full resolution depth testing on the primitives or primitive fragments identified as not requiring a read of the depth buffer without reading the depth buffer.

18 . A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of the coarse depth test hardware as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the coarse depth test hardware.

19 . A method of performing coarse depth testing in a graphics processing system in which a rendering space is subdivided into a plurality of tiles, the method comprising:

receiving a set of one or more primitives or a set of one or more primitive fragments related to a tile of the plurality of tiles;

obtaining a depth range for the tile, the depth range for the tile identifying a depth range based on primitives or primitive fragments previously processed for the tile; and

for at least one primitive in the set of one or more primitives or at least one primitive fragment in the set of one or more primitive fragments:

making a determination, based on the depth range for the tile, as to whether the primitive or the primitive fragment is in front of the primitives or primitive fragments previously processed for the tile according to a depth compare mode, and

in response to making a determination that the primitive or a primitive fragment is in front of the primitives or primitive fragments previously processed for the tile, identifying the primitive or the primitive fragment as not requiring a read of a depth buffer to perform full resolution depth testing.

20 . A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the method as set forth in claim 19 .

Assignments (1)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →
Priority Claims (2)
GB 1908807 · Jun 19, 2019 · national
GB 1908812 · Jun 19, 2019 · national
Continuity (2)
Continuation 17516274 · Nov 1, 2021
Continuation 16906170 · Jun 19, 2020
References Cited (29)
US 6646639B1 · Greene et al. · 2003 [cited by applicant]
US 7023437B1 · Voorhies et al. · 2006 [cited by applicant]
US 7333106B1 · Wu et al. · 2008 [cited by applicant]
US 9576396B2 · Park · 2017 [cited by examiner]
US 9922450B2 · Morphet · 2018 [cited by applicant]
US 20020196252A1 · Liao et al. · 2002 [cited by applicant]
US 20050122338A1 · Hong et al. · 2005 [cited by applicant]
US 20060209078A1 · Anderson et al. · 2006 [cited by applicant]
US 20080170066A1 · Falchetto · 2008 [cited by applicant]
US 20100007662A1 · Cox et al. · 2010 [cited by applicant]
US 20120299910A1 · Liang · 2012 [cited by applicant]
US 20140176544A1 · Fishwick et al. · 2014 [cited by applicant]
US 20140354654A1 · Heggelund et al. · 2014 [cited by applicant]
US 20150161815A1 · Andersson et al. · 2015 [cited by applicant]
US 20150363968A1 · Yang et al. · 2015 [cited by applicant]
US 20160005208A1 · Liao et al. · 2016 [cited by applicant]
US 20160098856A1 · Broadhurst et al. · 2016 [cited by applicant]
US 20160098858A1 · Broadhurst et al. · 2016 [cited by applicant]
US 20160239939A1 · Kakarlapudi et al. · 2016 [cited by applicant]
US 20170091987A1 · Morphet · 2017 [cited by applicant]
US 20180082431A1 · Andersson et al. · 2018 [cited by applicant]
US 20180082469A1 · Andersson et al. · 2018 [cited by applicant]
US 20180082488A1 · Akenine-Moller et al. · 2018 [cited by applicant]
US 20180349315A1 · Heggelund et al. · 2018 [cited by applicant]
GB 2510964B · 2015 [cited by applicant]
GB 2524121B · 2016 [cited by applicant]
WO 0070561A1 · 2000 [cited by applicant]
Akenine-Moeller et al., “Graphics for the Masses: A Hardware Rasterization Architecture for Mobile Phones,” Computer Graphics Proceedings, Jul. 2003, pp. 801-808. [cited by applicant]
Anderson et al., “Masked Depth Culling for Graphics Hardware,” ACM Transactions on Graphics, vol. 34, No. 6, Oct. 2, 2015, pp. 1-9. [cited by applicant]