Downscaler and Method of Downscaling
A hardware downscaler and an architecture for implementing a FIR filter in which the downscaler can be arranged for downscaling by a half in one dimension. The downscaler can comprise: hardware logic implementing a first three-tap FIR filter; and hardware logic implementing a second three-tap FIR filter; wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter.
1 . A hardware downscaler, for downscaling by a half in one dimension, the downscaler comprising:
hardware logic implementing a first three-tap finite impulse response (FIR) filter; and
hardware logic implementing a second three-tap FIR filter;
wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter.
2 . The hardware downscaler of claim 1 , wherein each three-tap filter is implemented to perform its constituent multiplications using only bit shift operations.
3 . The hardware downscaler of claim 1 , wherein each three-tap filter is implemented with filter coefficients that are integer powers of 2.
4 . The hardware downscaler of claim 1 , wherein each three-tap filter is implemented with filter coefficients of ¼, ½, ¼.
5 . The hardware downscaler of claim 1 , further comprising hardware logic for implementing a decimation.
6 . The hardware downscaler of claim 5 , wherein the hardware logic for implementing the decimation is integrated with the hardware logic implementing the second three-tap FIR filter.
7 . A hardware architecture for implementing a FIR filter with 2 N +1 binomial coefficients, where N is an integer and N>1, the architecture comprising:
a series of N three-tap FIR sub-filters ( 312 , 314 );
wherein, for every n, where n is an integer from 1 to N−1, the architecture is configured to provide the output from the nth one of the sub-filters as an input to the (n+1)th sub-filter.
8 . The hardware architecture of claim 7 , wherein each sub-filter is implemented with filter coefficients of ¼, ½, ¼.
9 . The hardware architecture of claim 7 , where each sub-filter is implemented to perform its constituent multiplications using only bit shift operations.
10 . A computer-implemented method for downscaling data by a half in at least one dimension, the method comprising:
providing data as an input to hardware logic implementing a first three-tap finite impulse response (FIR) filter;
performing, at the hardware logic implementing the first three-tap FIR filter, a first filtering operation;
providing an output from the hardware logic implementing the first three-tap FIR filter to hardware logic implementing a second three-tap FIR filter;
performing, at the hardware logic implementing the second three-tap FIR filter, a second filtering operation.
11 . The computer-implemented method of claim 10 , wherein the hardware logic implementing each three-tap filter uses only bit shift operations to perform the multiplication operations of the respective three-tap filter.
12 . The computer-implemented method of claim 10 , wherein each three-tap filter is implemented with filter coefficients that are integer powers of 2.
13 . The computer-implemented method of claim 10 , wherein the each three-tap filter is implemented with filter coefficients of ¼, ½, ¼.
14 . The computer-implemented method of claim 10 , further comprising using hardware logic to implement a decimation.
15 . The computer-implemented method of claim 14 , wherein the hardware logic for implementing the decimation is integrated with the hardware logic implementing the second three-tap FIR filter.
16 . A computer-implemented method for filtering data with a finite impulse response (FIR) filter having 2 N +1 binomial coefficients, where N is an integer and N>1, the method comprising:
Filtering the data through hardware logic implementing a series of N three-tap FIR sub-filters; and
wherein, for every n, where n is an integer from 1 to N−1, the filtering comprises providing the output from the nth one of the sub-filters as an input to the (n+1)th sub-filter.
17 . The computer-implemented method of claim 16 , wherein each sub-filter is implemented with filter coefficients of ¼, ½, ¼.
18 . The computer-implemented method of claim 16 , where each sub-filter is implemented to perform its constituent multiplications using only bit shift operations.
19 . A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware downscaler as set forth in claim 1 , that when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware downscaler.
20 . A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware architecture for implementing a FIR filter as set forth in claim 7 , that when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware architecture for implementing a FIR filter.