Hierarchical acceleration structures for use in ray tracing systems
Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data. Ray tracing systems and computer-implemented methods for performing intersection testing in the ray tracing system determine whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.
1 . A computer-implemented method of generating a hierarchical acceleration structure in a ray tracing system, the method comprising:
storing data representing the hierarchical acceleration structure, wherein a node of the hierarchical acceleration structure is an implicitly represented node, which is implicitly represented by said stored data;
wherein data representing the implicitly represented node is not explicitly included as part of said stored data but can be inferred from said stored data using at least some of the data representing at least some nodes of the hierarchical acceleration structure.
2 . The method of claim 1 , wherein said at least some nodes of the hierarchical acceleration structure are nodes which are the descendants of the implicitly represented node at a particular level in the hierarchical acceleration structure.
3 . The method of claim 2 , wherein either:
(i) the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure are the children of the implicitly represented node in the hierarchical acceleration structure, or
(ii) the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure are the grandchildren of the implicitly represented node in the hierarchical acceleration structure.
4 . The method of claim 2 , wherein regions represented by nodes of the hierarchical acceleration structure are axis-aligned bounding boxes in the scene, and wherein the data representing the implicitly represented node can be inferred by determining, in each dimension of the scene, a minimum and a maximum component of the components defining the axis-aligned bounding boxes represented by the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure.
5 . The method of claim 1 , wherein stored data representing the hierarchical acceleration structure comprises data indicating how nodes of the hierarchical acceleration structure are linked, and wherein the data representing the implicitly represented node can be inferred from said stored data using at least some of the data indicating how the nodes of the hierarchical acceleration structure are linked.
6 . The method of claim 1 , wherein said storing data representing the hierarchical acceleration structure comprises storing said data representing the hierarchical acceleration structure in data blocks, wherein a data block comprises data representing a sub-tree within the hierarchical acceleration structure, wherein the sub-tree comprises one or more nodes at a plurality of levels within the hierarchical acceleration structure.
7 . The method of claim 6 , wherein the data block comprises: (i) data defining regions represented by the nodes at the lowest level of the sub-tree, and (ii) data indicating how the nodes of the sub-tree are linked.
8 . The method of claim 7 , wherein a node of the sub-tree which is at a level above the lowest level of the sub-tree is the implicitly represented node which is implicitly represented by the data in the data block, such that data defining the region represented by the implicitly represented node is not explicitly stored in the data block but can be inferred from: (i) at least some of the data defining the regions represented by at least some of the nodes at the lowest level of the sub-tree, and (ii) at least some of the data indicating how the nodes of the sub-tree are linked.
9 . The method of claim 8 , wherein the implicitly represented node is the parent node in the sub-tree for said at least some of the nodes at the lowest level of the sub-tree.
10 . The method of claim 6 , wherein the data block comprises data defining regions which are represented by nodes having a shared ancestor in the hierarchical acceleration structure.
11 . The method of claim 10 , wherein the shared ancestor is a shared parent, a shared grandparent or a shared great grandparent in the hierarchical acceleration structure.
12 . The method of claim 10 , wherein the data block comprises an indication of a common origin region and wherein the data in the data block defining the regions which are represented by nodes having a shared ancestor in the hierarchical acceleration structure comprises, for each of the nodes having the shared ancestor, one or more offsets from the common origin region, wherein the common origin region represents the region represented by the shared ancestor.
13 . The method of claim 6 , wherein said storing data representing the hierarchical acceleration structure comprises storing said data representing the hierarchical acceleration structure in a memory, wherein said stored data can be read from the memory for use in intersection testing in the ray tracing system, and wherein the size of a data block matches the minimum burst size of the memory.
14 . The method of claim 1 , wherein said storing data representing the hierarchical acceleration structure comprises storing said data representing the hierarchical acceleration structure in a memory, wherein said stored data can be read from the memory for use in intersection testing in the ray tracing system.
15 . A method of rendering an image of a scene in a ray tracing system comprising:
generating a hierarchical acceleration structure according to the method as set forth in claim 1 ;
performing intersection testing using at least part of the generated hierarchical acceleration structure; and
executing one or more shader programs to process results of the intersection testing to determine rendered values representing the image of the scene.
16 . A processor configured to generate a hierarchical acceleration structure in a ray tracing system, the processor being configured to:
cause data representing the hierarchical acceleration structure to be stored,
herein a node of the hierarchical acceleration structure is an implicitly represented node, which is implicitly represented by said data; and
wherein data representing the implicitly represented node is not explicitly included as part of said stored data but can be inferred from said stored data using at least some of the data representing at least some nodes of the hierarchical acceleration structure.
17 . The processor of claim 16 , wherein at least some nodes of the hierarchical acceleration structure are nodes which are the descendants of the implicitly represented node at a particular level in the hierarchical acceleration structure.
18 . A ray tracing system configured to render an image of a scene, the ray tracing system comprising:
a processor configured to generate a hierarchical acceleration structure as set forth in claim 16 ;
an intersection testing module configured to use at least part of the generated hierarchical acceleration structure to perform intersection testing; and
processing logic configured to execute one or more shader programs to process results of the intersection testing to determine rendered values representing the image of the scene.
19 . A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processor which is configured to generate a hierarchical acceleration structure in a ray tracing system, the processor being configured to:
cause data representing the hierarchical acceleration structure to be stored, wherein a node of the hierarchical acceleration structure is an implicitly represented node, which is implicitly represented by said data; and
wherein data representing the implicitly represented node is not explicitly included as part of said stored data but can be inferred from said stored data using at least some of the data representing at least some nodes of the hierarchical acceleration structure.