IP Library Granted Patent US 12,367,046
Granted Patent B2
US 12,367,046 · App. 18/075,394 · Granted Jul 22, 2025

Scheduling tasks using swap flags

Inventors: Simon Nield (Kings Langley, GB); Yoong-Chert Foo (Kings Langley, GB); Adam de Grasse (Kings Langley, GB); Luca Iuliano (Kings Langley, GB)
Assignee: Imagination Technologies Limited
G06F9/3016G06F7/575G06F9/3001G06F9/3009G06F9/30185G06F9/3836G06F9/3851G06F9/3867G06F9/3887G06F9/522
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Quick Facts
Patent No.
US 12,367,046
App. No.
18/075,394
Granted
Jul 22, 2025
Kind
B2
Abstract

A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.

Claims (10)

1. A method of scheduling instructions within a processing unit comprising:

in response to determining that a swap flag in a decoded instruction is set, triggering a scheduler to de-activate a scheduled task prior to execution of said decoded instruction.

2. The method according to claim 1 , further comprising:

in response to determining that the swap flag in the decoded instruction is not set, sending the decoded instruction to an ALU (Arithmetic Logic Unit) targeted by the decoded instruction.

3. An instruction controller comprising:

hardware logic arranged in response to determining that a swap flag in a decoded instruction is set, to trigger a scheduler to de-activate a scheduled task.

4. The instruction controller according to claim 3 , further comprising:

hardware logic arranged in response to determining that the swap flag in the decoded instruction is not set, to send the decoded instruction to an ALU (Arithmetic Logic Unit) targeted by the decoded instruction.

5. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller comprising:

hardware logic arranged in response to determining that a swap flag in a decoded instruction is set, to trigger a scheduler to de-activate a scheduled task prior to execution of said decoded instruction.

Assignments (1)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
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