Dynamic power measurement using formal
Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.
1. A system to verify that an integrated circuit defined by a hardware design meets a power requirement, the system comprising:
a hardware monitor including
one or more transition detection logic units, the one or more transition detection logic units configured to detect whether a power consuming transition has occurred with one or more flip-flops of an instantiation of the hardware design,
one or more counter update logic units in communication with the one or more transition detection logic units, the one or more counter update logic units configured to count a number of power consuming transitions detected by the one or more transition detection logic units, and
a property verification logic unit configured to determine whether the power requirement is met at a particular point in time by evaluating one or more properties related to power consuming transitions based on the number of power consuming transitions counted by the one or more counter update logic units;
a scenario defined in a formal verification language; and
a formal verification tool configured to formally verify whether the integrated circuit defined by the hardware design meets the power requirement for the scenario using the hardware monitor;
wherein the hardware design, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the integrated circuit.
2. The system of claim 1 , wherein at least one of the one or more transition detection logic units is configured to detect a flip-flop transition of a flip-flop of the instantiation of the hardware design.
3. The system of claim 2 , wherein the at least one of the one or more transition detection logic units is configured to detect a flip-flop transition of a flip-flop of the instantiation of the hardware design by monitoring an output signal of the flip-flop to detect a change in the output signal.
4. The system of claim 3 , wherein the at least one of the one or more transition detection logic units is configured to detect a change in the output signal by comparing a present value of the output signal to a previous value of the output signal.
5. The system of claim 1 , wherein at least one of the one or more transition detection logic units is configured to detect a clock transition of a flip-flop of the instantiation of the hardware design.
6. The system of claim 5 , wherein the at least one of the one or more transition detection logic units is configured to detect a clock transition of a flip-flop of the instantiation of the hardware design by monitoring a clock trigger signal of the flip-flop and detecting a change in the clock trigger signal.
7. The system of claim 6 , wherein the at least one of the one or more transition detection logic units is configured to detect a change in the clock trigger signal by comparing a present value of the clock trigger signal to a previous value of the clock trigger signal.
8. The system of claim 1 , wherein the one or more properties comprises a property that compares the count of the power consuming transitions to a maximum number of power consuming transitions defined by the power requirement.
9. The system of claim 8 , wherein the one or more properties comprises a property that states that the count of power consuming transitions is less than or equal to the maximum number of power consuming transitions.
10. The system of claim 1 , wherein the one or more properties comprises a property that compares the count of power consuming transitions to a count of power consuming transitions for another hardware design.
11. The system of claim 10 , wherein the one or more properties comprises a property that asserts that the count of power consuming transitions is less than or equal to the count of power consuming transitions for the other hardware design.
12. A method of verifying that an integrated circuit defined by a hardware design meets a power requirement, the method comprising:
detecting, by a hardware monitor, whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design;
in response to detecting that a power consuming transition has occurred, updating, by the hardware monitor, a count of power consuming transitions for the instantiation of the hardware design;
determining, whether the power requirement is met at a particular point in time by evaluating one or more properties related to power consuming transitions based on the count of power consuming transitions for the instantiation of the hardware design; and
formally verifying the one or more properties for a predefined scenario using a formal verification tool;
wherein the hardware design, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the integrated circuit.
13. The method of claim 12 , wherein the one or more properties comprises a property that compares the count of power consuming transitions to a maximum number of power consuming transitions defined by the power requirement.
14. The method of claim 12 , wherein the one or more properties comprises a property that the compares the count of power consuming transitions for the hardware design to a count of power consuming transitions for another hardware design.
15. A non-transitory computer readable storage medium having stored thereon computer readable instructions, that when executed at a computer system, cause the computer system to perform the steps of the method as set forth in claim 12 .
16. A system to verify that an integrated circuit defined by a hardware design has an operating characteristic which meets an operating requirement, the system comprising:
a hardware monitor including
one or more event detection logic units, the one or more event detection logic units configured to detect an occurrence of an event which is indicative of the operating characteristic in an instantiation of the hardware design, and
a property verification logic unit configured to determine whether the operating requirement is met at a particular point in time by evaluating one or more properties related to an operating characteristic based on whether the one or more event detection logic units have detected the occurrence of an event which is indicative of the operating characteristic in the instantiation of the hardware design;
a scenario defined in a formal verification language; and
a formal verification tool configured to formally verify whether the integrated circuit defined by the hardware design meets the operating requirement for the scenario using the hardware monitor;
wherein the hardware design, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the integrated circuit.