IP Library Granted Patent US 8,103,866
Granted Patent B2
US 8,103,866 · App. 12/018,062 · Granted Jan 24, 2012

System for reconfiguring a processor array

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,103,866
App. No.
12/018,062
Granted
Jan 24, 2012
Kind
B2
Abstract

Embodiments of the invention are directed to a system for reconfiguring a processor array while it is currently operating. The reconfiguration system uses configuration chains streamed down communication channels that are set for the re-configuration process, then re-set after the reconfiguration process has completed.

Claims (32)

1. A system for reconfiguring elements in a multi-element processor array, comprising:

a series of processors;

a programmable connection network linking the series of processors by communication channels;

a reconfiguration operator operable on a first processor and structured to receive a reconfiguration command and retrieve a reconfiguration stream;

a configuration stream operator structured to parse the reconfiguration stream into a local component and components for subsequent processors; and

a network reconfigurator operable on the first processor and structured to use a portion of the local component to program the connection network into a reconfiguration network.

2. The system of claim 1 , further comprising:

a hold process structured to prevent data from passing through at least one of the communication channels.

3. The system of claim 2 , in which the at least one of the communication channels is upstream from the first processor.

4. The system of claim 1 , further comprising:

a flush process structured to remove data passing through at least one of the communication channels.

5. The system of claim 1 in which the communication channels comprise at least one a protocol register in each of the communication channels.

6. The system of claim 1 , in which the network reconfigurator is also structured to reprogram the connection network into an operating network.

7. A method for re-configuring elements in a multi-element processor array that is already presently operating, comprising:

acquiring reconfiguration data;

coupling individual processors through communication channels set as reconfiguration channels;

loading local reconfiguration data into a local processor;

sending downstream reconfiguration data to downstream processors across the reconfiguration channels; and

after receiving an indication that the downstream processors have been reconfigured, setting the communication channels to be execution channels.

8. The method of claim 7 , further comprising:

receiving a request to reconfigure the processor array.

9. The method of claim 7 , further comprising:

accessing an external memory that stores the reconfiguration data.

10. The method of claim 7 , further comprising:

after the indication has been received that the downstream processors have been reconfigured, starting the local processor.

11. The method of claim 7 , further comprising:

removing from the reconfiguration data configuration components for an associated memory processor; and

passing the configuration components for an associated memory processor to the associated memory processor.

12. The method of claim 7 , further comprising:

issuing a hold command to prevent data from passing through at least one of the communication channels.

13. The method of claim 12 , further comprising:

issuing a flush command to cause at least one of the communication channels to remove data.

Assignments (6)
SECURITY INTEREST Recorded Jul 31, 2024
From: IMAGINATION TECHNOLOGIES LIMITED
To: FORTRESS INVESTMENT GROUP (UK) LTD
Reel/Frame 068221/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2013
From: NETHRA IMAGING, INC.
To: METAGENCE TECHNOLOGIES LIMITED
Reel/Frame 031576/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2013
From: METAGENCE TECHNOLOGIES LIMITED
To: IMAGINATION TECHNOLOGIES LIMITED
Reel/Frame 031576/0540 →
SECURITY AGREEMENT Recorded Jun 30, 2010
From: NETHRA IMAGING, INC.
To: ARM LIMITED
Reel/Frame 024611/0288 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2009
From: AMBRIC, INC.
To: NETHRA IMAGING INC.
Reel/Frame 022399/0380 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2008
From: BUTTS, MICHAEL R.
To: AMBRIC, INC.
Reel/Frame 020953/0500 →