Method and apparatus for use in the design and manufacture of integrated circuits
A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.
1. An apparatus implemented in one or more processors and configured to generate a representation of an integrated circuit for performing integer division x/d where x is a variable integer and d is an invariant integer constant, the apparatus comprising:
a parameter creator configured to derive an integer triple (a,b,k) which satisfies Round(x/d)=(ax+b)/2 k for a desired rounding mode; and
a synthesis tool configured to generate the representation of the integrated circuit from a representation of the logical operation (ax+b)/2 k in accordance with the derived integer triple (a,b,k) for manufacture of the integrated circuit.
2. The apparatus of claim 1 , wherein the parameter creator is configured to derive an integer triple (a,b,k) which has a minimum value of k to satisfy Round(x/d)=(ax+b)/2 k for the desired rounding mode.
3. The apparatus of claim 1 , wherein the parameter creator is configured to derive a value for b from values of a and k, the derived value of b having the smallest Hamming weight of the possible values of b satisfying Round(x/d)=(ax+b)/2 k .
4. The apparatus of claim 1 , further comprising a representation generator configured to derive the representation of the logical operation (ax+b)/2 k using the derived integer triple (a,b,k).
5. The apparatus of claim 4 , wherein the representation generator is an RTL (Register Transfer Level) generator, and the representation of the logical operation (ax+b)/2 k is an RTL representation.
6. The apparatus of claim 1 , wherein the desired rounding mode is one of: (i) round towards zero, (ii) round to nearest, and (iii) faithful rounding.
7. The apparatus of claim 1 , wherein the parameter creator is further configured to derive k differently for different rounding modes.
8. The apparatus of claim 1 , wherein the parameter creator is further configured to receive n, d, and the desired rounding mode as inputs, wherein x is an n-bit number.
9. The apparatus of claim 1 , wherein the parameter creator is configured to derive the integer triple (a,b,k) based on a set of conditions.